CPLD: collapse

Hallo,

in an CPLD-Design (XC95??XL), I have 2 data-strobe signals, and a data-stobe-select-signal. The selected strobe should clock 2*16 input regs:

input [15:0] pinoekels; reg [15:0] di1; reg [15:0] di2; wire strobe = (ssel && s1) || (ssel && s2);

always @(posedge strobe) begin di1

"Jan Bruns":

These device have only one "product term" for clocks. Sorry.

Gruss

Jan Bruns

By looking at your code. It is an synchronous design. CPLD will not gives good performance for asynchronous design because of their architectures.

If possible, you should try clock enable signal instead of directly drive the register's clk.

I think the XC9500 does not have "negedge" flip-flops. Thues it has to use inverted feedback clock to trigger the flip-flops with negtive edge.

Looks like your're right.

But the 9500XL have a programmable clock-inverter.

Gruss

Jan Bruns

"Kar":

Hmja.

clk = ATA udma_in_dev_strobe && ATA_PIO_in_strobe; ce = strobeenable; // ATA udma_in_dev_strobe is multiplexed with "IORDY"

is not exactly what I planned to implement, but solved the problem.

Gruss

Jan Bruns