VHDL to schematic conversion

Hi Khansa,

Mentor Graphics HDL designer has a code-to-graphics option (good for looking at the hierarchy), for gate level most synthesis tools (Synplify/Precision/Spectrum) have a RTL/Gatelevel schematic viewer. I am not sure about Orcad though,

Hans.

Xilinx ISE Webpack, which can be downloaded from Xilinx website, offer such an option. It's called Schematic Viewer. It's not as good as the

Hendra

I assume what you are looking for is a tool that will take RTL and create a schematic at the RTL level, or at the gate level with a netlist, without a synthesis step. If you synthesize it, it will look totally different then a RTL schematic of the same circuit. You can use the Undertow Suite source code debugging set of software to do this. This software is also a fraction of the cost of a synthesis tool, and is very easy to use. The Undertow Suite will display a schematic of Verilog, VHDL, mixed Verilog and VHDL and SystemVerilog. You can download this software from

Robert Schopmeyer/Veritools, Inc.

khansa wrote: