Field-Programmable Gate Arrays

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ISE 7.1 unisims and cver simulation

Hi all, Up to now i've been using ISE 6.3 together with gplcver for simulation. Some things seem to have changed with I...
1 comments posted 21yrs
posted by ico
1 comments posted 21yrs posted by ico

ISA vs. patent/trademark

Hi, Are ISA covered by patents or trademarks? Is it allowed to develop a processor core for a popular ISA as long as no...
46 comments posted 21yrs
posted by "eric UNDERSCORE delage AT yahoo DOT fr"
46 comments posted 21yrs posted by "eric UNDERSCORE delage AT yahoo DOT fr"

Book?

When one has read a beginner/introduction book of VHDL what is a good second book to read? And where to go next? (Studen...
2 comments posted 21yrs
posted by blabla
2 comments posted 21yrs posted by blabla

ucf timing constraint question

NET "cp100" TNM_NET = "cp100"; TIMESPEC "TS_cp100" = PERIOD "cp100" 10 ns HIGH 50 % INPUT_JITTER 400 ps; TIMEGRP "cp100...
0 comments posted 21yrs
posted by geeja
0 comments posted 21yrs posted by geeja

Protection measurements

Hy Lets assume we run a C program on the FPGA. This program contains a loop which executes EXACTLY n times. How can I m...
1 comments posted 21yrs
posted by ernte23
1 comments posted 21yrs posted by ernte23

Quartus 5

Any information regarding new Quartus 5.0 and NIOS II? rick
1 comments posted 21yrs
posted by me
1 comments posted 21yrs posted by me

DCM LOCKED as reset

Hi, Can DCM's LOCKED o/p signal be used as reset within FPGA? is this scheme feasible :- PowerON Reset acts as DCM rese...
3 comments posted 21yrs
posted by manishr
3 comments posted 21yrs posted by manishr

WebPack_7.1 on Linux ?

Hi all, Xilinx claimed that their WebPack_ISE run under RHEL. Is anybody successfully install it on common Linux distro...
1 comments posted 21yrs
posted by habib
1 comments posted 21yrs posted by habib

Structural vs Behavioral

Both of the following 2 always blocks should synthesize to a decoder. always @(address) case (address) 2'b00 : row = 4'...
9 comments posted 21yrs
posted by u1000393
9 comments posted 21yrs posted by u1000393

Stupid question

Is there any way of using the Xilinx toolchain on a Mac? I have become spoiled by my Mac Mini, and unpacking my loud PC...
13 comments posted 21yrs
posted by twomack
13 comments posted 21yrs posted by twomack

Need Help

Hello al I am working on the design of a simple RAM module for m microcontroller design. In the VHDL simulation data is...
2 comments posted 21yrs
posted by vasantm
2 comments posted 21yrs posted by vasantm

Reverse engineering ASIC into FPGA

Does anyone have experience with reverse engineering ASIC (black box) into equivelant FPGA devices (pin equivelant with...
34 comments posted 21yrs
posted by weingart
34 comments posted 21yrs posted by weingart

IBUFG and BUFG +xilinx

Hello Guys, I had a doubt about the IBUFG and BUFG in xilinx. 1.I have connected clock from oscillator to CLKG IO of th...
5 comments posted 21yrs
posted by stud_lang_jap
5 comments posted 21yrs posted by stud_lang_jap

Xilinx XPower - Accuracy Information

Hello i'm from germany and just registered to this forum. Hello to everybod out there I'm working on very small FPGA De...
6 comments posted 21yrs
posted by werbung
6 comments posted 21yrs posted by werbung

ML310 z-dok connectors

Hi anyone out there know where I can get z-dok connectors(tyco part number 1367555-1) for less than $72AUD or $55USD ea...
0 comments posted 21yrs
posted by wing.fong.wong_remove_me_
0 comments posted 21yrs posted by wing.fong.wong_remove_me_