Xilinx ISE Input Pins Problem

Hi All, I was wondering is there any way to synthesis a design of mine on an FPGA using the ISE tool so that I can get results for area speed, xpower and such. It is a partial prooduct summation tree that adds 13

12-bit numbers in a weighted manner. The tool tries to assign its input and output ports to pins and i get a worning to say that more than 100% of the device is used up even though it only uses 8% of the gates. I was wondering is there a way to unbond the ports from the pins. I was thinking just box it up and buffer it but not sure.

Thanks Keith

Reply to
Keith_eng_fyp
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Build a little (13*12)-step shift register taking input from one of the pins, and with its stages connected to the inputs of your summation tree; I imagine that'll be small enough not to make a nonsense of the area/speed/power results. You probably do want to take all the outputs to pins, otherwise the optimiser will be clever.

Tom

Reply to
Thomas Womack

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