Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

sharing a common resource... potential problems...

if i am having a set of modules which reference some common control registers and each of these modules can read or wri...
2 comments posted 21yrs
posted by Puneetsingh81
2 comments posted 21yrs posted by Puneetsingh81

Functional vs, Timing

Hi out there, maybe someone can give her/his opinion: I have the following assignment in my top level file: entiy top i...
2 comments posted 21yrs
posted by ALuPin
2 comments posted 21yrs posted by ALuPin

different I/O buffers available inXilinx FPGA

could anyone please explain me the difference between the buffers IBUF OBUF BUFGP BUFGDLL BUFT etc available in XILINX F...
9 comments posted 21yrs
posted by bajajk
9 comments posted 21yrs posted by bajajk

ISE Testbench/Schematic Generation ignores package

Using the Xilinx Project Navigator, I created a project and added a package definition (vhd-file) at the very top level...
1 comments posted 21yrs
posted by ha.schulz
1 comments posted 21yrs posted by ha.schulz

Soft CPU vs Hard CPU's

Hai all, I heard that the SOFT CPU's have wide range of benefits than the HARD CPU's. if so, then why still HARD CPU's a...
15 comments posted 21yrs
posted by nkishorebabu123
15 comments posted 21yrs posted by nkishorebabu123

clock input over an I/O pin

Hi I was wondering if anyone has any advice or experience on th following I need to clock some logic with a clock signa...
4 comments posted 21yrs
posted by arthur
4 comments posted 21yrs posted by arthur

Help OPB <> Wishbone wrapper

Hallo, I should connect the wishbone can core with opb bus. I have downloaded from asics.ws the wrapper. There is someo...
1 comments posted 21yrs
posted by marcotoschi_no_spam
1 comments posted 21yrs posted by marcotoschi_no_spam

free-ip

Over the last couple of weeks I have tried accessing the web site www.free-ip.com and gotten an error message. Is it mi...
3 comments posted 21yrs
posted by florin
3 comments posted 21yrs posted by florin

Internal clk gen on IO PAD in Xilinx FPGA

Hi All Someone can generate internal clock inside fpga using IO PAD Smth like this IBUF_inst: IBUF port map (I => ClkGe...
0 comments posted 21yrs
posted by leevv
0 comments posted 21yrs posted by leevv

ANN: USB/FPGA board with programmer's interface

We would like to announce the availability of our XEM3001 Xilinx Experimentation Module and accompanying FrontPanel sof...
0 comments posted 21yrs
posted by info
0 comments posted 21yrs posted by info

Xilinx TMRTool price

Hi All, I couldn't find any information regarding the price of Xilinx's new TMRTool. Does anybody happen to be intereste...
1 comments posted 21yrs
posted by amrahmadain
1 comments posted 21yrs posted by amrahmadain

Connecting Virtex2pro to Virtex4 via RocketIO MGT's

The following extract from the Virtex 4 RIO user guide states: */Serialization/* */As in Virtex-II Pro X devices, Virte...
5 comments posted 21yrs
posted by jason.stubbs
5 comments posted 21yrs posted by jason.stubbs

Fitting functionality in an XC2VP30 FPGA.

Dear All, I am trying to establish if I can fit the following functionality into a single FPGA. I have FPGA resource ut...
10 comments posted 21yrs
posted by simon.stockton
10 comments posted 21yrs posted by simon.stockton

tools used for ASIC synthesis

Hai all, can you plz let me know the different tools used in industry for ASIC SYNTHESIS regards, kishore
2 comments posted 21yrs
posted by nkishorebabu123
2 comments posted 21yrs posted by nkishorebabu123