Field-Programmable Gate Arrays

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Altera DSP dev board stratix II

I download my design via byteblaster USB. The leds wink and blink as if the fpga is taking the data. At the end of down...
1 comments posted 21yrs
posted by nospam
1 comments posted 21yrs posted by nospam

Free VHDL Analysis Tool (vhdlarch 0.1.0)

I started building a VHDL analysis tool tentatively called VhdlArch. http://www.confluent.org/wiki/doku.php?id=vhdlarch...
3 comments posted 21yrs
posted by tom1
3 comments posted 21yrs posted by tom1

Flowcharts and diagrams

Hi, I'm looking for a freeware or low cost program do document and illustrate the signal processing flow in my FPGA des...
8 comments posted 21yrs
posted by usenet
8 comments posted 21yrs posted by usenet

"The ISE 7.1 Experience"

Hello group. Regrettably, I just installed 7.1 in my computer in order to try the implementation of one of my designs i...
5 comments posted 21yrs
posted by pablo.N
5 comments posted 21yrs posted by pablo.N

PPC405 Performance Monitoring

Hello, Is there a way to do performance monitoring on the PPC405 in the Virtex II Pro? I am specifically interested in...
9 comments posted 21yrs
posted by amahar
9 comments posted 21yrs posted by amahar

Embedded MicroBlaze solution

Hi, ALL! Recently one of my friends faced very strange problem. He had the MicroBlaze CPU in his design running with 50...
5 comments posted 21yrs
posted by v_mirgorodsky
5 comments posted 21yrs posted by v_mirgorodsky

Xilinx VIIPro power supplies

I'm using a VII Pro in a current project which requires the use of the RocketIO. This runs on 2.5V and I've selected a...
14 comments posted 21yrs
posted by enquiries
14 comments posted 21yrs posted by enquiries

help neeeded for byteblaster of altera

hi i m a student working in quartus II environment.i wnated to desig my own byteblaster can anybody help me out.i have...
1 comments posted 21yrs
posted by smital_2002us
1 comments posted 21yrs posted by smital_2002us

Reading old F2.1i schematics

I'm sure others have this problem ... Is there a tool that'll let one view and hopefully print a schematic done in the...
8 comments posted 21yrs
posted by Bassman59a
8 comments posted 21yrs posted by Bassman59a

LUT in fpga

Hi all, I am new to FPGA architecture. To know the what does LUT means I came across few good articles posted in this g...
9 comments posted 21yrs
posted by am.imak
9 comments posted 21yrs posted by am.imak

Timing and synthesis problem+xilinx

Hello, I am using virtex 2 pro for a design of mine. When i am implementing the synethesized edf using ISE it is giving...
1 comments posted 21yrs
posted by stud_lang_jap
1 comments posted 21yrs posted by stud_lang_jap

virtex4 reconfiguration time

Fcclk max = 100 MHz bitstream of VLX25 = 7.4 Mbit SelectMAP port width = 32 bits so the minimum reconfiguration time fo...
9 comments posted 21yrs
posted by stephane
9 comments posted 21yrs posted by stephane

Regarding driving of SCL and SDA pins of I2C

Hi all, This is a basic qustion regarding SDA and SCL pins. Since both these pins are bidirectional these should pins n...
14 comments posted 21yrs
posted by praveen.kantharajapura
14 comments posted 21yrs posted by praveen.kantharajapura

opb_ethernet timing constraints

Hi, I'm using EDK 6.3i under linux (release 12.3) and I'm trying to instantiate an ethernet controller on my virtex 4 b...
2 comments posted 21yrs
posted by bertrand.rousseau
2 comments posted 21yrs posted by bertrand.rousseau