Internal clk gen on IO PAD in Xilinx FPGA

Hi All

Someone can generate internal clock inside fpga using IO PAD

Smth like this

IBUF_inst: IBUF port map (I => ClkGenExt, O => ClkGenInt);

nClkGenInt nClkGenInt, T => '0', O = ClkGenExt); BUFG_inst: BUFG port map (I => ClkGenInt, O => Clk);

Even better, we can use UPAD (unbonded IO PAD, that exist almost i

every package). Then we don't need to search for unused IO pin o schematic

Clock freq will be aroud 200 MHz and depends mostly on current driv

strenth of OBUFT. Of course, it'll drift with temperature, but fo some application it can be usefull. For example, we'd like to reus some old board for new project and we are missing externa oscillator. "Bad" clk is still better then nothing

My question is, due to the advanced ChipSync feature of Virtex4, ca

we create some kind of stable clk generator in IO PAD with flexibl freq range

Second question is about UPAD. I didn't find any on V4FX12FG668. Is i

due to specific V4 architecture, or it's not present in smalles device of the family