if i am having a set of modules which reference some common control registers and each of these modules can read or write to these registers then there is a severe problem of 'bus' first of all and secondaly the 'mode' of the control registers(INOUT??). Is there any design reference or document that may be of help to me?
The first thing I would do is re-think the design approach. Having multiple writers of a resource is usually just a bad idea. If the situation is that different modules write to mutually exclusive bits of the registers, then you just need to break these registers up into separate registers.
If the writers are trully writing to the same bits, and this is really what you want (see the start of my reply), then you could do something like have multiple registers, and then mix their outputs (OR, AND, priority, ...). The problem really comes down to what happens if 2 or more writers both try to write at the same time. How is this resolved. A complex solution to this might be something like a separate module for these annoying registers, that takes in a bus and a write request from each of the writers. Inside this module is where you decide what to do with simultaneous writes.
On the third had, re-think, and change your design approach.
Philip Freidin
Philip Freidin Fliptronics
Hi Philip, As per ur suggestion, i tried out something different and also mixing outputs by ORing them together has helped to some extent. Now i am giving final touches to the design, hope it works. The basic module is working fine. Thanx for the answers. regards, puneet
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