Field-Programmable Gate Arrays

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Declining a job offer

I just got my first job offer with a semiconductor company. I am yet to sign the paperwork. I am hoping to get more off...
13 comments posted 21yrs
posted by shuss3
13 comments posted 21yrs posted by shuss3

DSP-PC architectural advice needed.

Hello, I have an idea for a design of a data aquisition system and i am willing to verify the possibility to implement...
4 comments posted 21yrs
posted by marcsok
4 comments posted 21yrs posted by marcsok

Tutorial on FPGAs

Somebody published nice tutorial on FPGAs. Describes architecture, logic blocks and routing in common FPGAs. http://www....
1 comments posted 21yrs
posted by gupta.gaurav
1 comments posted 21yrs posted by gupta.gaurav

Missing post

I've posted a question to the newsgroup a few days ago about some Virtex2 DCI problem I have, the post seems to have di...
2 comments posted 21yrs
posted by jakab.tanko
2 comments posted 21yrs posted by jakab.tanko

combining two EDF netlist in ISE

Hello guys, I am working on a project which contain some IP core which is avaiable to me in EDF netlist form. I am havi...
3 comments posted 21yrs
posted by stud_lang_jap
3 comments posted 21yrs posted by stud_lang_jap

Altera logic programmer card

Hi, Does anyone know where I can get hold of an Altera Logic programmer card (lp6). Any info appreciated. Cheers Alan.
1 comments posted 21yrs
posted by alan
1 comments posted 21yrs posted by alan

Odd Oversampling

Hi newsgroup, maybe someone of you out there has faced some similar problem: I want to sample 16MHz data with a 125MHz...
12 comments posted 21yrs
posted by ALuPin
12 comments posted 21yrs posted by ALuPin

debugging source code for PowerPC

Hi, I am trying to debug a simple application which is running on a powerpc. I can set breakpoints (in gdb) and run unt...
0 comments posted 21yrs
posted by someone
0 comments posted 21yrs posted by someone

Multi-page schematics (.bdf) in Quartus II?

Can someone please tell me how to make a multi-page schematic in Altera's Quartus II software? I can't seem to find any...
5 comments posted 21yrs
posted by LeonardGabrielson
5 comments posted 21yrs posted by LeonardGabrielson

SPROM JTAG confusion!

Hello, I'm currently working on a project and I am at the stage where I'm ready to work on the PCB layout. For developm...
1 comments posted 21yrs
posted by aosik5
1 comments posted 21yrs posted by aosik5

Microblaze Functions (Xilinx Specific)

While programming using Microblaze, I used a scanf function to read data from an input port. But I get a compilation er...
2 comments posted 21yrs
posted by fpga00
2 comments posted 21yrs posted by fpga00

MAX7000S CPLD tri-state OE delay

I'm interfacing a 2kx8 15ns CMOS SRAM (IDT6116SA15TP) to an Altera EPM7128SLC84-15 CPLD to implement a very simple CPU....
0 comments posted 21yrs
posted by andrew
0 comments posted 21yrs posted by andrew

FPGA/Embedded courses online or near Toronto

Hi, are there any fpga/embedded/pcb design courses online or in toronto that i as a newbie could take as a newbie. I'm...
3 comments posted 21yrs
posted by zalzon
3 comments posted 21yrs posted by zalzon

Spartan 3E slower that Spartan 3?

Hello guys, I just made a quick speed test in ISE 7.1 with a Spartan 3E device. A 32-bit counter runs at 129 MHz in XC3...
30 comments posted 21yrs
posted by george.mercury
30 comments posted 21yrs posted by george.mercury

The DLP from Texas Instruments...

For the switches that route signals in an FPGA, ideally, one wants something that does not delay signals, even if it ta...
4 comments posted 21yrs
posted by jsavard
4 comments posted 21yrs posted by jsavard