I'm interfacing a 2kx8 15ns CMOS SRAM (IDT6116SA15TP) to an Altera EPM7128SLC84-15 CPLD to implement a very simple CPU. Data and program will be stored in the SRAM which is pre-loaded via JTAG using JAM STAPL.
My problem is the CPLD output buffer enable / disable delays (tZX / tXZ) which - being of the order of 7ns - are going to cause data bus contention. I'm driving the lpm_bustri OE signal and the SRAM /OE pin from (opposite senses) of the same logic. It takes the CPLD 7ns to tri-state the data bus, and the SRAM starts driving it 0ns (zero nanoseconds) after /OE is asserted.
At the moment, all my RAM control signals (address, /oe, /we) change together - albeit a few nS after the rising clock edge - and the data bus tri-states a further 7ns behind them. One way to bring things into line might be to delay the other signals through LCELLs; but that would use up macrocells, and Help says not to use LCELL for delays.
Is there another (better) way?
BTW my clock frequency is 20 MHz.