Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15255 Threads Posts
to

Worth reading in Field-Programmable Gate Arrays

VHDL or Verilog

Hello I have a very basic question. Normally you have the choice if you want to use VHDL or Verilog for describing you...
6 comments posted 21yrs
posted by ernte23
6 comments posted 21yrs posted by ernte23

CAM for FPGA ...

Hi all, I would like to get into a CAM design for FPGA. Does any of you know about where can I find material on this su...
12 comments posted 21yrs
posted by Moti.cohen
12 comments posted 21yrs posted by Moti.cohen

ATA FPGA IP Core

We would like to interface a DSP, TMS320C67xx, to an ATA-5 harddisk directly. It must run in DMA mode (instead of PIO)....
1 comments posted 21yrs
posted by digitalsignal999
1 comments posted 21yrs posted by digitalsignal999

LVDS pin assignment

Hi, I am designing the following converter: LVDS -> some processing -> LVDS. Each LVDS Interface has 3 channels and 1 c...
4 comments posted 21yrs
posted by benjamin
4 comments posted 21yrs posted by benjamin

Power Estimation without Pad Connection (XPower)

Hi I want to make a XPower Estimation of a Design which has no connectio to the pins/pads of the FPGA. I tried to do th...
1 comments posted 21yrs
posted by werbung
1 comments posted 21yrs posted by werbung

AHDL and quartus II simulation

Hi, To design an Altera Stratix FPGA I use a top level AHDL file. But using AHDL I found a pretty strange behaviour (at...
0 comments posted 21yrs
posted by haribeau
0 comments posted 21yrs posted by haribeau

Bug in DDR template in Lattice FPGAs ?

Hi, I am trying to use the "DDR_MEM" Lattice template which is responsable for the datapath for DDR SDRAM controller. "...
9 comments posted 21yrs
posted by ALuPin
9 comments posted 21yrs posted by ALuPin

Unconstrained ports for synthesis

Hi all, I am having a component Multiplier with unconstrained ports. But this is not my top_level_entity and ports are...
5 comments posted 21yrs
posted by am.imak
5 comments posted 21yrs posted by am.imak

And gate in Neural Network

Hi People, I am interested to build AND gate (as neural network) using FPGA. I am using Xilinx webpack 7. If anyone can...
1 comments posted 21yrs
posted by xiibweb
1 comments posted 21yrs posted by xiibweb

Ambigous operator '&'

HI all, While compiling my design in Quartus II 4.2 , I got following errors. The piece of code is given below.... Erro...
3 comments posted 21yrs
posted by am.imak
3 comments posted 21yrs posted by am.imak

Cost of Altera DSP Builder

Hi All, Been trying to find out the cost of Altera DSP Builder 3.0.0. Can't find any pricing info anywhere on web (also...
1 comments posted 21yrs
posted by no
1 comments posted 21yrs posted by no

avnet dev. kit flash reprogram

Hello, I have been working on a Virtex II Pro Development kit from Avnet. I tried running a custom compiled linux on th...
0 comments posted 21yrs
posted by sirishka_no_spam
0 comments posted 21yrs posted by sirishka_no_spam

College Project

I am an electrical engineering student who has been tasked to create short game using WinCUPL. We are expected to set u...
4 comments posted 21yrs
posted by pocketdoor
4 comments posted 21yrs posted by pocketdoor