Field-Programmable Gate Arrays

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OV6620 PCLK CLK

Hi, I am using OV6620 Omnivision CMOS Image sensor. My module has CLK fosc: 17.734MHz PCLK: 112ns = 8.92MHz Does any bod...
1 comments posted 21yrs
posted by archilleswaterland
1 comments posted 21yrs posted by archilleswaterland

Perl Preprocessor for HDL

Because of the deficiencies in Verilog or the tools, I often have to write Perl to generate Verilog. Examples of these...
7 comments posted 21yrs
posted by kevin_neilson
7 comments posted 21yrs posted by kevin_neilson

actel blockram the easy way?

Is there an easy to use Actel's internal ram without going to coregen? I'm concerned about compatibility issues if I hav...
3 comments posted 21yrs
posted by xin.zheng
3 comments posted 21yrs posted by xin.zheng

Linux, ISE 7.1, problems, problems, problems ....

ok, ok we've beaten this subject to death already .... I just had this really radical and crazy idea: XILINX, how about...
3 comments posted 21yrs
posted by russelmann
3 comments posted 21yrs posted by russelmann

UCF File - How to define this Constraint?

Hello I am using Synopsys fc2_shell and the Xilinx ISE 6.1 Tools to creat my FPGA-Design. When I define a clock frequen...
0 comments posted 21yrs
posted by werbung
0 comments posted 21yrs posted by werbung

Strange FPGA problem

Hello, I am integrating an IP core and i am facing a strange problem. One of the register of the IP core which is R/W r...
3 comments posted 21yrs
posted by stud_lang_jap
3 comments posted 21yrs posted by stud_lang_jap

Spartan 3E availability

Hi all, Have people had reasonable success getting samples of Spartan3E parts? The XS3S100E, for example. I ask this bec...
2 comments posted 21yrs
posted by brad1
2 comments posted 21yrs posted by brad1

Can't find folder

Hi, I tried to install ISE 7.1 machine and ran into some problem. But now my project which was in the folder C:/Xilinx...
0 comments posted 21yrs
posted by ann.lai
0 comments posted 21yrs posted by ann.lai

source control and Xilinx ISE 6 and 7

My quick seach shows that this question comes up occasionally but never seems to get a decent answer. First, though, an...
20 comments posted 21yrs
posted by Bassman59a
20 comments posted 21yrs posted by Bassman59a

Problem installing ISE 7.1

Hi, I am having a problem installing Xilinx ISE 7.1. It completed 99% and then it says "The following error was encount...
0 comments posted 21yrs
posted by ann.lai
0 comments posted 21yrs posted by ann.lai

[Info]Platform USB.

Just got my new Xilinx platform usb download cable. $149. Works great, even with 6.3.03, very fast. No longer will I ne...
2 comments posted 21yrs
posted by symon_brewer
2 comments posted 21yrs posted by symon_brewer

OPB to Wishbone Wrapper

Hallo, I should connect the wishbone can core with opb bus. I have downloaded from asics.ws the wrapper. There is someo...
0 comments posted 21yrs
posted by marcotoschi_no_spam
0 comments posted 21yrs posted by marcotoschi_no_spam