Hi,
-- Error messages are......
Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(26): ports must be constrained Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(27): ports must be constrained Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(28): ports must be constrained Error: Can't elaborate user hierarchy "Core:Core_Map|Datapath:Datapath_Map" Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 0 warnings Error: Processing ended: Wed Apr 20 16:33:52 2005 Error: Elapsed time: 00:00:05
-- My Multiplier component is ......... entity Multiplier_Synth is port( Op1 : in signed; -- Operator 1 Op2 : in signed; -- Operator 2 Mult_Out : out signed -- Multiplication Result ); end entity Multiplier_Synth;
architecture Multiplier_Synth_Arch of Multiplier_Synth is begin Mult_Out Mux1_Out, Op2 => Mux2_Out, Mult_Out => Mult_Out );
Mux1_Out , Mux2_Out and Mult_Out are constrained signals . Hence Op1,Op2,Mult_Out implicitly can be constrained by bit length of
20,20,40 respectively.
Thanks..
-- Mohammed A Khader.