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LVDS pin assignment

Hi,

I am designing the following converter: LVDS -> some processing -> LVDS. Each LVDS Interface has 3 channels and 1 clock channel at about 300 MHz (differential clock rate).

My question is if I should use GLCK pins for the incoming LVDS clock?

Should I also use GLCK pins for the outgoing LVDS clock? I don't think so, because there is no OBUFGDS. Or does it make sense to use GCLK pins for OBUFDS?

Another question is the bank assignment. Should I put the complete Interface (both LVDS) on the same bank? Or better each LVDS on its own bank? Or do banks not matter at all?

regards, Benjamin

Reply to
Benjamin Menküc
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Let us see if I can provide you with some guidance,

Aust> Hi,

Yes. Use an IBUFG for the clock, using a dedicated clock input pin. These have the lowest skew (delay) to get in the chip).

No such thing. Any OBUF can duplicate a clock by using the DDR FF. Tie the top FF D input to a '1', and the bottom FF D input to a '0', and on the rising edge you will get an outgoing rising edge, and on the falling edge you will get an outgoing falling edge.

All clocks internally should be on a BUFG so they may drive any IOB FF, or any CLB FF with the least skew. I don't think

Yes. This is the least skew (delay) from the data bits to the clock (if they are adjacent). Or better each LVDS on its own

Nope. Too much skew possible. Or do banks not matter at all? They do matter.

Reply to
Austin Lesea

Hi Austin,

thanks for the answer.

How can I set the FF connections in the IOBs manually? In the lib.pdf I find only how to instantiate an OBUF, however I can only choose an input and output there.

With this construction I have only a single clock, not a differential clk_n and clk_p. Is this correct?

Shouldn't I generate the differential outgoing clock signal using a OBUFDS where I have just the clk_n or clk_p input.

regards, Benjamin

Reply to
Benjamin Menküc

Hello

I think you should, if you want full LVDS link.

About input LVDS pair clock... It could be placed in ordinary input pair I/O P&N, don't forget about termination resistors on PCB.

Look at Phase Alignment on xilinx website, 300MHz is not a toy. Best regards Jerzy Gbur

Reply to
Jerzy Gbur

Here is code snippet for generating clock using DDR filpflops and LVDS output.

clkn clk_out, C0 => clk, C1 => clkn, CE => '1', D0 => '1', D1 => '0', R => '0', S => '0' );

Use LVDS buffers for clk_out signal. In UCF file lock the location of atleast the clk_out_p which is the P output of the LVDS signal.

U2 : OBUFDS_LVDSEXT_33 port map( I => clk_out, O => clk_out_p, OB => clk_out_n );

I think its not necessary to instantiate the LVDS buffer. If you chose the drive type as LVDS in the UCF file, its automatically taken care of. Need to cross check.

Brijesh

Reply to
Brijesh

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