Hi,
To design an Altera Stratix FPGA I use a top level AHDL file. But using AHDL I found a pretty strange behaviour (at least it seems so to me). Following is the relevant extract from the AHDL file:
subdesign top ( x[31..0] : bidir; }
variable xtri[31..0] : tri;
begin xtri[] = B"11001100110011001100110011001100"; end;
when I synthesize the design and load it to the FPGA things work as expected (the pins represented by x[] hold the assigned "11001100..." sequence.
But when I simulate the design in quartus II (Processing -> Start Simulation) with a predefined vwf file x is not set. All the values stay "U Z" all the time.
This is pretty different behaviour of simulation and FPGA implementation, isn't it? What I'd expect is the behavior the FPGA displays.
thanks for any hint on how to get the simulation run as expected,
/ch