Field-Programmable Gate Arrays

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how to put an FIR in an FPGA?

I wrote a synthesizeable 4 tap FIR code in vhdl and synthesized it using Xilinx. I have an Xess XSV board with Virtex 8...
1 comments posted 21yrs
posted by nashafi
1 comments posted 21yrs posted by nashafi

is the 8051 architecture public domain?

Lots of companies have 8051 compatible chips... the best known are Atmel, Dallas, Philips, Siemens. Does that mean thes...
0 comments posted 21yrs
posted by jeannicolle
0 comments posted 21yrs posted by jeannicolle

playxsvf file501b

Hi, I have just recently updated to ISE7.1. I used to be able to use playxsvf file just fine, but now when I use it, it...
1 comments posted 21yrs
posted by ann.lai
1 comments posted 21yrs posted by ann.lai

"Implement Design" Error on ISE 6.3 webpack

I'm getting an error during the translate portion of the implement design section and I have no clue what it is about:...
1 comments posted 21yrs
posted by arlencox
1 comments posted 21yrs posted by arlencox

DDR SODIMM on Avnet Virtex II PRO development kit

Hi all, I'm working on a ADS-XLX-V2PRO-DEVP20-6 (The Xilinx Virtex 2 PRO development kit from Avnet, with a XC2VP20 onb...
20 comments posted 21yrs
posted by ascgroup_nospamme
20 comments posted 21yrs posted by ascgroup_nospamme

Time Borrowing

Hi all, I came accross the concept of Time Borrowing, which I have been trying to understand from a week. Google search...
2 comments posted 21yrs
posted by sams235
2 comments posted 21yrs posted by sams235

Xilinx multiplier out of slices

Hi, I'm new to the Xilinx tools. How do I tell Xilinx ISE 7.1 to synthesise the following statement: y
4 comments posted 21yrs
posted by psommerfeld
4 comments posted 21yrs posted by psommerfeld

Virtex 4 Power consumption

Can anyone give me an estimate of the max current a V4fx60 FPGA will draw for VCCINT @ 1.2v, & VCCAUX and VCCO @ 2.5v?...
19 comments posted 21yrs
posted by jason.stubbs
19 comments posted 21yrs posted by jason.stubbs

A PC for make synthesis

I need to buy a new PC. What is the best processor for saving time during synthesis projects? AMD Athlon 64 Intel XEON I...
9 comments posted 21yrs
posted by marcotoschi_no_spam
9 comments posted 21yrs posted by marcotoschi_no_spam

OCM interface to SDRAM

Hello all, I would like to know whether an interface like an OCM interface is possible at all for the SDRAM !!! Thank yo...
4 comments posted 21yrs
posted by johnsons
4 comments posted 21yrs posted by johnsons

Virtex-4 Routing

Hi, I can't seem to find any documentation on Virtex-4 routing, no even a general schematic, i looked at the datasheets...
1 comments posted 21yrs
posted by mlmsilva
1 comments posted 21yrs posted by mlmsilva

Speed acceleration !!!

Hello I am using a Virtex2Pro board and lately I was trying to use the PowerPC at the highest speed (300MHz) on my boar...
4 comments posted 21yrs
posted by johnsons
4 comments posted 21yrs posted by johnsons

Writing to Ram

Hello, i am using an Xilinks Spartan 3 XC3S200 FPGA. What i am trying to do is write to the Ram on this board (256K by...
0 comments posted 21yrs
posted by amir.intisar
0 comments posted 21yrs posted by amir.intisar

ispTRACY-Lattice vs. SignalTap-Altera

Hi newsgroup, can someone explain to me which architecture characteristics of Lattice EC vs. Altera Cyclone lead to the...
1 comments posted 21yrs
posted by ALuPin
1 comments posted 21yrs posted by ALuPin