how to put an FIR in an FPGA?

I wrote a synthesizeable 4 tap FIR code in vhdl and synthesized it using Xilinx. I have an Xess XSV board with Virtex 800 fpga on it. I am new to FPGA programming. Can some one guide me what steps i have to take to implement my FIR on this board .

I believe steps will be synthesize Implement generate bit file

using xilinx ISE software

But I used an example to implement a & segment LCD counter and i am confused about the functionality of ucf file and how to make one for my design i.e how i can configure inputs and outputs of my design so that i can send an input and see what is the response as an out put on the LCD



Reply to
Loading thread data ...

Take a look at the Constraint Guide ($XILINX\doc\usenglish\books\docs\cgd\cgd.pdf) installed with your ISE software. The constraint for placing pins is "LOC".

HTH, Jim (remove capital letters)

formatting link

Reply to
Jim Wu

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.