OCM interface to SDRAM

Probably not. What parts are you using?

BCD

Joey wrote:

possible

Hi BCD,

I didn't really understand what you meant with what parts I am using.

I am trying to implement a C program which is a little big. I tried it with the local BRAMs and now I want to know whether I can really route the signals out of the FPGA chip and to the peripherals on the board. I just wanted to make the onboard SDRAM as the place for my program !! So the plan is, to fetch the program from the SDRAM interface. Somehow I cannot increase the Bus frequency more than 100MHz. But the SDRAM might work faster and thats why I am trying to do this.

Thank you Joey

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Joey,

I asked about the parts because the OCM interface changed from V2Pro to V4.

If you're using V2Pro, you can't do it. If you're using V4, you probably still can't do it, but I can't say for sure...although I'm sure someone else can tell you with certainty.

Regardless of which parts you're using, I think you're best bet is to put the SDRAM off the PLB bus.

BCD

In Virtex2Pro, the OCM data must return in a fixed number of clock cycles. This obviously isn't a good match to external DRAM memory especially since refresh can take lots of cycles. I checked in the Virtex4 PowerPC docs and only the DSOCM has added "Optional support for variable latency for read or write data transfer" specifically to support "wide range of new applications utilizing memory-mapped I/O" (page 140:

In addition, the EDK memory controllers already have plb or opb interfaces on them so you'd have to develop an OCM-interfaced memory controller. Not super difficult but using the provided controllers should get you up and running very quickly. Then you can determine what additional system-level architectural changes are appropriate for your application.

Don't forget to enable the PowerPC405 caches--they make a large difference and do note that OCM accesses bypass the PowerPC405 caches.

Paul

Joey wrote: