Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15255 Threads Posts
to

Worth reading in Field-Programmable Gate Arrays

ispTRACY-Lattice vs. SignalTap-Altera

Hi newsgroup, can someone explain to me which architecture characteristics of Lattice EC vs. Altera Cyclone lead to the...
1 comments posted 21yrs
posted by ALuPin
1 comments posted 21yrs posted by ALuPin

Timing Reports Xilinx.....Max. freq of operation?

Hi all... After i synthesize my code i get the following timing reports in my synthesis report file. Minimum period: 11...
2 comments posted 21yrs
posted by Puneetsingh81
2 comments posted 21yrs posted by Puneetsingh81

Looking for a RocketIO expert in Ottawa, ON

Just as the subject says I am looking for someone local who has experience in using RocketIO and possibly Aurora protoco...
0 comments posted 21yrs
posted by mbmsv
0 comments posted 21yrs posted by mbmsv

JTAG and SPROM for Spartan II-e

I'm currently laying out a PCB containing a Spartan II-E (XC2S200E PQ208). I'm laying out the circuitry for an SPROM ch...
2 comments posted 21yrs
posted by aosik5
2 comments posted 21yrs posted by aosik5

PPCs sharing an OCM BRAM

I have run into a roadblock with my project. Trying to get the PPCs in the V2P to share a BRAM. I have gotten it to wor...
3 comments posted 21yrs
posted by joeylrios
3 comments posted 21yrs posted by joeylrios

Xilinx Impact in Linux 2.6.x

Have anyone got Impact working in Fedora Core 3? Or any similar Linux? I have tried this: http://www.fpga-faq.org/FAQ_P...
12 comments posted 21yrs
posted by nospam
12 comments posted 21yrs posted by nospam

HDL in safety critical applications

Are there any official documents dealing with HDLs (Hardware description languages like VHDL, Veriolog, SystemC,...) in...
2 comments posted 21yrs
posted by salewski
2 comments posted 21yrs posted by salewski

low budget SystemC to VHDL Compiler?

Does anybody know a SystemC to VHDL Compiler with a reasonable price? Maybe special prices for universities? Falk S.
0 comments posted 21yrs
posted by salewski
0 comments posted 21yrs posted by salewski

FIFO as a Logic Analyzer; Clock synthesizer

Hi! I have a big FIFO chip covered by dust, that I'd like to finally use. The most useful application I'm imagining for...
5 comments posted 21yrs
posted by nospam
5 comments posted 21yrs posted by nospam

parts needed: XC4VLX40-10FF668CES

Help! We need to obtain qty. 20 of the above Virtex 4 parts as our distributor is unable to deliver within our schedule...
0 comments posted 21yrs
posted by schellho
0 comments posted 21yrs posted by schellho

xilinx ml310 + linux + System.map file problem

Hi Buddies, I am running montavista linux on ml310 and its fine.But each time I make new build (kernel Image), I see Sy...
0 comments posted 21yrs
posted by reddy.jagadeesh
0 comments posted 21yrs posted by reddy.jagadeesh

Simulation in modelsim.... Multiple Drivers.......

Hi all... i have been trying to simulate some code in which there is a data bus that is declared to be of INOUT type. I...
4 comments posted 21yrs
posted by Puneetsingh81
4 comments posted 21yrs posted by Puneetsingh81