Latest threads in Field-Programmable Gate Arrays

Timing Reports Xilinx.....Max. freq of operation?

Hi all... After i synthesize my code i get the following timing reports in my synthesis report file. Minimum period: 11...

2 21yrs

Puneetsingh81

2 21yrs Puneetsingh81

Looking for a RocketIO expert in Ottawa, ON

Just as the subject says I am looking for someone local who has experience in using RocketIO and possibly Aurora protoco...

0 21yrs

mbmsv

0 21yrs mbmsv

JTAG and SPROM for Spartan II-e

I'm currently laying out a PCB containing a Spartan II-E (XC2S200E PQ208). I'm laying out the circuitry for an SPROM ch...

2 21yrs

aosik5

2 21yrs aosik5

PPCs sharing an OCM BRAM

I have run into a roadblock with my project. Trying to get the PPCs in the V2P to share a BRAM. I have gotten it to wor...

3 21yrs

joeylrios

3 21yrs joeylrios

Xilinx Impact in Linux 2.6.x

Have anyone got Impact working in Fedora Core 3? Or any similar Linux? I have tried this: http://www.fpga-faq.org/FAQ_P...

12 21yrs

nospam

12 21yrs nospam

HDL in safety critical applications

Are there any official documents dealing with HDLs (Hardware description languages like VHDL, Veriolog, SystemC,...) in...

2 21yrs

salewski

2 21yrs salewski

low budget SystemC to VHDL Compiler?

Does anybody know a SystemC to VHDL Compiler with a reasonable price? Maybe special prices for universities? Falk S.

0 21yrs

salewski

0 21yrs salewski

FIFO as a Logic Analyzer; Clock synthesizer

Hi! I have a big FIFO chip covered by dust, that I'd like to finally use. The most useful application I'm imagining for...

5 21yrs

nospam

5 21yrs nospam

Xilinx ISE Warning: FF/Latch <> is unconnected in block <>

Hi there, I created a CPLD design which works perfect in simulation, but does not work in hardware. There are many warn...

2 21yrs

nospam

2 21yrs nospam

parts needed: XC4VLX40-10FF668CES

Help! We need to obtain qty. 20 of the above Virtex 4 parts as our distributor is unable to deliver within our schedule...

0 21yrs

schellho

0 21yrs schellho

Is Cyclone-2 EP2C5 or EP2C8 available? If not, when?

I have an application that will probably use a XC3S200 part (probably only half filled). I need moderate DSP capability...

1 21yrs

jcc

1 21yrs jcc

Do Synplify DSP and Accelchip support multiple clock domains?

Question as subject. Can't find anywhere that explicitly says one way or the other so was wondering if anyone here knows...

5 21yrs

no

5 21yrs no

xilinx ml310 + linux + System.map file problem

Hi Buddies, I am running montavista linux on ml310 and its fine.But each time I make new build (kernel Image), I see Sy...

0 21yrs

reddy.jagadeesh

0 21yrs reddy.jagadeesh

Simulation in modelsim.... Multiple Drivers.......

Hi all... i have been trying to simulate some code in which there is a data bus that is declared to be of INOUT type. I...

4 21yrs

Puneetsingh81

4 21yrs Puneetsingh81

VHDL or Verilog

Hello I have a very basic question. Normally you have the choice if you want to use VHDL or Verilog for describing you...

6 21yrs

ernte23

6 21yrs ernte23

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