multiplier with one fixed value other user defined

Hi,, I am interested to write a code in VHDL where one input is user defined and the other input is fixed to some value....

for example

here two in fixed (which I want to define as fixed). and 0 , 1, 2 , 3 user defined.

This code is generated using Xilinx webpack...

================================================================ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity multo is Port ( p1 : in std_logic_vector(1 downto 0); w1 : in std_logic_vector(1 downto 0); ou : out std_logic_vector(3 downto 0)); end multo;

architecture Behavioral of multo is

begin

ou