I can't seem to find any documentation on Virtex-4 routing, no even a general schematic, i looked at the datasheets and user guides but nothing. I saw a answer record that said that there weren't any TBUF's, and the data sheet shows that there is a switch matrix similar to Virtex-II in the CLB's. Does anyone have more information about it? is it similar to Virtex-II? When does Xilinx plan to release this information? Those who have ISE 7.1 can see FPGA Editor is there considerable differences?