Latest threads in Field-Programmable Gate Arrays

Strange behavior with counter (decreases instead of increasing)

Hello all. I have a very strange thing happening with my FPGA. I have Xilinx Spartan-3E FPGA, that I am programming to...

3 14yrs

3610

3 14yrs 3610

Interface Xilinx KC705 to BeagleBone?

I'm playing with the idea of interfacing a BeagleBone (cheap dual ARM Cortex A8 board) to a Xilinx KC705 Kintex develop...

16 14yrs

pete_fraser

16 14yrs pete_fraser

FPGA basic devtool options and prices?

I know this is a complex issue and that tool providers won't talk loud about it, but Im trying to find effective tools...

1 14yrs

mleikvol

1 14yrs mleikvol

FPGA + HDMI 1080P

I'm looking for a FPGA board that can support HDMI/DVI 1080P in/out. I'd like to avoid building my own, I'm probably loo...

3 14yrs

jprovidenza

3 14yrs jprovidenza

Xilinx UCF: Adding "Virtual Grounds"

Hi, Quick question. I want to connect a number of FPGA I/Os to ground without changing my VHDL i.e. via a constraint in...

5 14yrs

moogyd

5 14yrs moogyd

Initializing inferred blockRAMs / ROMs without $readmemh (Synplify)

I've discovered that Synplify no longer requires the use of $readmemh / $re= admemb to initialize inferred blockRAMs or...

0 14yrs

kevin.neilson

0 14yrs kevin.neilson

use differential I/O simultaneously

Hi all, Are there any method to use differential I/O simultaneously? Firstly, route in_P + in_N pad to pad connects to...

2 14yrs

1

2 14yrs 1

What is best/good way to create a small delay with LCMXO2-1200ZE ev kit

I need a delay, lets say 10us. I could use a lot of counters to get it from clk, but there probably is a better solutio...

3 14yrs

sala.nimi

3 14yrs sala.nimi

Completely puzzled: Strange shift register behaviour

Hi, I am not an FPGA expert although this is not my first design. The problem that I am having for two days now, is tha...

20 14yrs

me

20 14yrs me

XAUI on V5 FX200T

I am trying to implement a 10G MAC/XAUI design on a Virtex 5 FX200T FPGA. I have tested the same design on a V5 LX100T...

0 14yrs

chethanzmail

0 14yrs chethanzmail

Possibility to use MGTREFCLK1P/MGTREFCLK1N as clock for user logic in Spartan 6?

Hi, Due to broken design of the FPGA board, I have the master clock available only at MGTREFCLK1P/MGTREFCLK1N pins. Is...

1 14yrs

wzab01

1 14yrs wzab01

RE: now what is this? iMPACT:2356 - Platform Cable USB firmware must be updated.

its been about 40 min and it is not even 1 % how did you solve your problem??? --http://compgroups.net/comp.arch.fpga/no...

0 14yrs

mehta.vishal.360

0 14yrs mehta.vishal.360

XC9500XL keeper ?

I just migrated a project from the XCV9500 to the XC9500XL, and am having some problems with keepers on the used inputs...

6 14yrs

jmelson

6 14yrs jmelson

accumulator (again)

Dear All, I'm not an expert in VHDL, i'm just a curious trying to solve a research problem with an FPGA. I'm using a 32...

33 14yrs

jmariano65

33 14yrs jmariano65

Generate a pulse with a definite width

hi is it a good practice to generate a pulse strobe in Verilog with this code? or do i need to write a fsm for such app...

8 14yrs

nba_baheri

8 14yrs nba_baheri

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