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Strange behavior with counter (decreases instead of increasing)

Hello all. I have a very strange thing happening with my FPGA.

I have Xilinx Spartan-3E FPGA, that I am programming to count external pulses in 1us time bins. The way I'm doing that, is I have a pulse index counter, that increments whenever there's a rising edge on the pulse counter. (No resetting, no enabling, etc.) Then I have another loop that checks the count on the pulse counter every 1us, and writes the "pulse index" to an off-board SDRAM chip.

So I have an always block like this:

always @(posedge pulse_in) begin pulse_index

Reply to
yhs2012
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Is the input pulse that you are measuring synchronized to the clock that you are using for the rest of the logic? If it is not synchronized, you will get timing violations occasionally. Counters can behave unpredictably with timing violations because different bits in the counter may have different delays due to placement and routing differences. Look up de-metastabilization for more info.

Good Luck, BobH

Reply to
BobH

This problem is well known. The usual solution is to use a gray-code counter.

The problem comes when you latch the value while it is changing, and one changes (or has routing delay) different from the other.

Gray code only changes one bit on each count, such that you always get one value or the next.

-- glen

Reply to
glen herrmannsfeldt

Problem solved!

I used a gray counter and I am getting no errors so far.

Thanks so much for your help guys. You guys rock!

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Reply to
yhs2012

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