1. Home
  2. Field-Programmable Gate Arrays
  3. Xilinx UCF: Adding "Virtual Grounds"

Xilinx UCF: Adding "Virtual Grounds"

Hi, Quick question. I want to connect a number of FPGA I/Os to ground without changing my VHDL i.e. via a constraint in the UCF file

I have tried a number of things without success:

NET GND LOC = "AA14" | IOSTANDARD = LVCMOS25; NET gnd_net LOC = "R8" | IOSTANDARD = LVCMOS25; NET "gnd_net" LOC = "AB14" | IOSTANDARD = LVCMOS25; NET "GND_NET" LOC = "W14" | IOSTANDARD = LVCMOS25; NET "ground" LOC = "Y14" | IOSTANDARD = LVCMOS25;

Please tell me there is a way to do this (and then tell me what it is :-) ) Thanks, Steven

Reply to
moogyd
Loading thread data ...

i.e. via a constraint in the UCF file

I thought someone might have replied by now.

The only method I can think of is to put a wrapper around your VHDL code, with the extra ground pins tied to GND, and to synthesise that.

--
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk
Reply to
Mike Perkins

At least in earlier versions, I did stuff like that with a separate UCF line for each thing I was trying to do. So, I didn't try to put a LOC and a PULLUP or PULLDOWN on the same line. But, the ground function is a CPLD feature that is not present on FPGAs, isn't that right?

Jon

Reply to
Jon Elson

i.e. via a constraint in the UCF file

You can't infer drivers from the .ucf file. If you want the gounded pins to act as "virtual grounds" to reduce ground bounce, then you need to add them to your design and assign them to zero.

If you really can't change the VHDL for some reason, then you can achieve the same thing using the FPGA editor, but that method is more painful.

Just out of curiosity, why don't you want to change the VHDL code?

-- Gabor

Reply to
Gabor

VHDL i.e. via a constraint in the UCF file

LVCMOS25;

LVCMOS25;

IOSTANDARD = LVCMOS25;

IOSTANDARD = LVCMOS25;

IOSTANDARD = LVCMOS25;

)

Hi All, I am using an FPGA evaluation board to prototype and ASIC, and I want to avoid (or at least minimize) changes to the RTL between ASIC and FPGA.

I was assuming that you could achieve what I wanted via UCF, but it looks like I was wrong :-(

Anyway, updates to VHDL it is.

Thanks, Steven

Reply to
moogyd

VHDL i.e. via a constraint in the UCF file

LVCMOS25;

LVCMOS25;

IOSTANDARD = LVCMOS25;

IOSTANDARD = LVCMOS25;

IOSTANDARD = LVCMOS25;

:-) )

(or at least minimize) changes to the RTL between ASIC and FPGA.

I was wrong :-(

Probably the easiest way to avoid changes from the ASIC version is to make a wrapper for the FPGA version that mostly instantiates and hooks up the existing ASIC design, and adds any FPGA-only infrastructure like virtual grounds, internal power-on resets, etc.

If I were doing this in Verilog, I'd probably use the preprocessor to ifdef the FPGA additions, but the wrapper works in any HDL.

-- Gabor

Reply to
Gabor

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.