Field-Programmable Gate Arrays

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Xilinx : Clock Swallowing

Our current design uses clock swallowing to obtain lower frequency clocks. I'd like to implement this clocking behaviou...
3 comments posted 21yrs
posted by luke.darnell
3 comments posted 21yrs posted by luke.darnell

SPI interface cpol & cpha

Hi all, In SPI interface if i see there are two signals cpol and cpha, which are used for differnet data transfer forma...
6 comments posted 21yrs
posted by praveen.kantharajapura
6 comments posted 21yrs posted by praveen.kantharajapura

wide ROM

Hi, I want a ROM in FPGA which is 85 bits wide, is it possible to have one? Thanks
2 comments posted 21yrs
posted by bxbxb3
2 comments posted 21yrs posted by bxbxb3

Microblaze interrupt problem

hello, I have a microblaze system with a uart and a timer (both produce interrupt).The interrupts are handled by intc.U...
0 comments posted 21yrs
posted by fpga00
0 comments posted 21yrs posted by fpga00

Universal logic modules vs NAND-like modules

Hi everyone, Is there a proper name to distinguish NAND-like universal modules from ordinary ones, that is, the ones fo...
17 comments posted 21yrs
posted by cferreira
17 comments posted 21yrs posted by cferreira

Serial communication

Hello, I have a system composed of a Cyclone device and an 8051-like CPU, which acts as a passive-serial configuration...
0 comments posted 21yrs
posted by wyderskiREMOVE
0 comments posted 21yrs posted by wyderskiREMOVE

FPGA design under Mac OS X ?

Are there any FPGA design tools which will run under Mac OS X? I've found that the Icarus Verilog simulator and synthes...
18 comments posted 21yrs
posted by rhn
18 comments posted 21yrs posted by rhn

Quartus II Fitter Problem

Hi, I have been using Altera Quartus II v4.2 SP1 for quite a long time. Recently, I have a problem that the fiiter chan...
3 comments posted 21yrs
posted by eerobert
3 comments posted 21yrs posted by eerobert

Virtex-II Switch Matrix Performance

Hi, I'm trying hard to speed-optimize an arithmetic function on a VII 4000 - 4 device, using ISE 7.1. I have minimized...
2 comments posted 21yrs
posted by knittel
2 comments posted 21yrs posted by knittel

floorplanning

hello, there seems to be a plethora of textbooks on VHDL/Verilog available. But what about floorplanning ? Are there any...
23 comments posted 21yrs
posted by lukasz
23 comments posted 21yrs posted by lukasz

microblaze and 64 bit memory over PLB bus

Hi anyone has made it own microblaze soc (eg not using ML401 derivate) where PLB is connected to microblaze OPB over br...
3 comments posted 21yrs
posted by antti
3 comments posted 21yrs posted by antti

Whats going on here?

Hi FPGA experts I am a little bit desperate. We have designed a hardware module in EDK 6.2 which was working properly o...
4 comments posted 21yrs
posted by grabherp23
4 comments posted 21yrs posted by grabherp23

Handling Interrupt

Hallo, I have made a microcontroller with keyboard (16 key). I have a C function to handle interrupt that comes from ke...
1 comments posted 21yrs
posted by marcotoschi_no_spam
1 comments posted 21yrs posted by marcotoschi_no_spam

Tristate-Master-Slave testbench description

Hi , I want to use the following component instantiation in my VHDL testbench: entity tb_test is end tb_test; architect...
5 comments posted 21yrs
posted by ALuPin
5 comments posted 21yrs posted by ALuPin

PowerPC and application in external RAM

Hi, I have made a bootloader which runs from BRAM on a PPC. Now I want to download an application into external RAM and...
3 comments posted 21yrs
posted by someone
3 comments posted 21yrs posted by someone