floorplanning

When you need to worry about floor planning.. you had better have a PhD. Its one of the black arts when you are concerned about arrival times ... its far better to let the tools do it for you in most cases, but there are occasions where the tools fall flat but then you only fix the fault not place the whole design.

That's also why there are a few books.. but not many I would suspect.

Simon

Funny that you think it takes a PhD to drive layout tools,

In olden days most chips were layed out by non degreed draftpeople who did not do the circuit design, but kinda knew what looks right.

There were at least 2 books for them, Motorola, and Tanner EDA both have IC layout books, still valid today for polygon editing and even floorplanning since its the same idea no matter who you worked for or even 3u v .2u just more rules and layers.

As for FPGA floorplanning, all I see is the (not much) help guides, never seen any books on it, they would date too quickly, knowledge is very specific to each family, even each member. It is a bit of a black art and takes alot of practice too. For my own tastes the manual draw flow is about 100x too slow to be practical except for critical repeated blocks.

Its probably worth doing some test layout work along the way to get a feel for what the tool will do with different options but the results vary so much with the smallest changes. Like throwing it all up in the air and see it land differently every time. When the timing is easy, the tool has 0 incentive to do better. When the timing is almost impossible, the tool has only heuristics to find a result and it never looks like what a person would produce.

In an empty design theres not much call for it, but in a tight packed design its already too late. But there is one time it is justified and that is when you have N copies of same mega cell that could be hand packed and stepped and repeated. It may not actually be much faster by the cell, but it most certainly can improve packing density and makes all copies more or less the same timing spec. Humans really can do better at highly structured layout but the tools will exhaust your patience pretty quickly.

Unless you are way over 120MHz I doubt you need it unless you know how to do it anyway.

johnjakson at usa dot com

I forgot to say that manual design is inherantly bottom up design which means you assemble objects and see their interactions as you edit them even if the logic is incomplete. The tools should not care as long as you believe the logic is correct.

But the FPGA layout tools don't like that, they insist on a complete design that interferes with what you are trying to accomplish.

I have been fighting this battle for 20+ years with EDA writers, they don't use their own tools the way some of us would wish, only in the proscribed way. At one time I did IC mask layout and had no way to turn DRC off which is like driving around with a cop in your passenger seat, only much worse!

I wonder how much demand there would be for a realy slick and commercial FPGA layout tool that had at least a basic model of the LUTs and wiring delays that could be correlated with actual devices. I have some ideas on this but other projects come 1st.

johnjakson at usa dot com

I disagree. If you need the performance, floorplanning can make a huge difference, especially in designs that are heavily data path. The automatic placement tools fall seriously short of what a human can do. No need for a PhD though. I find that floorplanning skill seem to be more of a inate ability thing: either you have it or you don't. Some people are really good at it from day one, while others never do get the knack regardless of how long they study it.

Floorplanning doesn't take a PhD. Datapath floorplanning is more like doing a jigsaw puzzle than anything else.

The tools can't and don't do a the best or even a very good job of placement. Not the fault of the vendors, it is a very hard problem to find the best answer in the general case. The tools do an acceptable job for most designs anymore. What humans can easily do is to find a very good answer, especially if the structure is regular or can be made to be regular, or if there is one key problem to solve.

For the first case, think about a simple datapath. The logic, when built into LUTs (and other elements) often can be made as a regular structure where each bit uses basically the same logic, and if this logic is placed the same for each bit, then the control lines can be short and regular as well. This can make for a fairly simple to implement, fairly optimal design. Datapath floorplanning is an "easy" problem, as it can be done by a computer program that completes in reasonable time. If you design enough datapaths, you could save time building up a library of elements and building from those. There are dathpath building tools for ASICs, and they have been around for almost a decade. Maybe in another decade someone will bring one out for FPGAs, as part of a high end FPGA tool.

For the second case, my most recent design is fairly low speed, ~50 MHz in a Spartan-3. At one point in time, I was getting a timing failure on a BlockRam -> some data path logic -> multiplier path. The only reason why this was failing was that the automatic placement put the BlockRam in one corner of the part and the multiplier in the far corner of the part. I'm not sure why the tools have such problems with the large blocks, but my experience is that the automatic placement of BlockRams and multipliers is often poor. The cure was simple: I fixed placed all the BlockRams and multipliers to something reasonable. I've also seen cases where, to meet timing, a LUT or FF had to be in a specific location or a few specific locations. The automatic placement would often get close, but close wasn't good enough.

-- Phil Hays Phil-hays at posting domain (- .net + .com) should work for email

The problem is that most users design top down.. and when it comes to profit.. it's top down. And I agree... quite a few years ago we used to argue with the vendors about the problems with their tools... But I am more philosophical these days.

Even if there was a basic model of an LUT, you would have to have a different model for each family.. and probably for each device... the skill in designing this is far more than the 'average' task... also using this would force limitations in families or devices... that's the opposite that any vendor wants.

And I think you summed it up perfectly.. nice concept.. but who has the time to do it for a minority of the users?

Simon

its

Performance is usually the best place for the tweak.. the problem with hand placing is that a placement for one family won't necessarily be any good for another.. and it will reach a point where within the same family.. placements won't necessarily be combatable IMO.

I would also agree with the you've either got it or not... that's why engineers still have jobs and we haven't all been replaced by computers.. hence the black art crack :-)

Floor planning is best learned by trial and error I think... I also suspect that most people are best ignoring it until the have to do otherwise.. debugging is best done at higher levels and ignorance can be bliss.. or at least let you sleep at night.

My best is to use Symplify... I build constraints into my VHDL and use Xilinx unisim to force certain placement or a particular grouping (usually for IO) and check the floor planner to make sure it does it. More than that.. I ignore.. especially if the timings are OK.. I don't have to go deeper or work weekends and I finish on time with confidence (and a pay check!)

Simon

"Maybe in another decade someone will bring one out for FPGAs, as part of a high end FPGA tool. "

How many dollars do you think such a productivity tool would be worth?

An ASIC guy will easily pay $100K for that sort of thing, I bet the average FPGA guy today would squirm at $5K. ASIC EDA tool developments are financed by VCs who expect a decent ROI. At few $k per seat, I see less chance of that even if volumes could be higher.

Now if what X is saying about make it your asic is true, then many more ASIC guys will be changing over to FPGA design flows, but the problem is tools, ASIC guys are used to high value high cost tools for 1M gate designs.

Well if FPGAs can do 1M equivalent size projects then will these ASIC guys want better more open tools or will they happily accept total vendor lock in. As an x ASIC guy I know the answer to that, they will hate it.

But I suspect if a Meta FPGA model can be built for each popular FPGA device, I could see some useful tools being built. Not sure if it will happen.

see other post on OSX

Since I only see FPGAs through Webpack eyes, I can't know what Synplicity, Mentor offerings can do for the floor planning pros. It keeps coming back to the synthesis, who is in charge of the vision thing, timing driven synthesis has no grand vision internally. For a decent high end floor planning tool, you would need to either work with that synthesis internals or just replace it with human driven placement and let the synthasis finish up whats left over.

In the past I suggested that schematic driven design (RIP) could easily be the basis of floorplanning, every schematic symbol drawn maps directly to an area of hand synthesied logic blocks, hiearchical driven design.

Since that approach is dead, I would now suggest using the output schematic that come from synthesis and annotate that with floor planning hints. The problem there is that those schematics are worse than what a 3yr old can draw.

As you said, when I make 16 copies of something, the average EE sees a bright light and draws an array and reduces the problem 2 fold, datapath plus control. The average dim witted tool (always written by PhDs no doubt) smashes away all logical structure and randomizes everything. Until the EDA tool guys understand this, the tools won't get better. If anything I believe they will get worse as FPGAs keep getting bigger.

The key with regularity is that for humans it drastically simplifies the solution N fold and makes things managable. For tools, its just more cycles.

end of rant

johnjakson at usa dot com transputer2 at yahoo dot com

Simon, I am not so sure the Meta model would have to be super accurate, just reasonably so.

It would have to describe the varying delays through LUTs, and switch fabric and cover the more obvious features available, probably in a HDL model. That automatically sets off alarm bells at the vendor since now anybody can see how their structures are built. Does anybody really care, its not like you can go fab a clone even if you have a detailed model of slice.

Even if the timing was 20% off, just being able to put FFs and adders and what not in the best possible place for datapath given this accuracy would be far better than the dim wit SW can do with likely not much better nos. Once the ucf or xcf file is sent back to the vendor tool, we can see if the result is better or not.

If the features can be openly described in the pdf spec, then it can be modelled and correlated with actual models in an automated fashion against the vendor tools.

In an ASIC, such foolery is limited since every bodies std cell library is basically the same.

johnjakson at usa dot com

You can probably expect FPGA guys to spend up to 35k maybe even 100k... cost of one engineer... too much and you have to look at the life time of the product and the return on capital

What will happen is the ASIC guys will retrain or end up working at MacDonnalds... Top down is a far better approact anyway.. at least the tools vendors will always tell you that.. and people leaning structured programming too.. bottom up will gradually become a forgotten aspect of design as the tools become good enough and the devices too fast. I have even put my OOP and strutured programming to work in my own designs... not as complex as Delphi OOP but same concepts apply.

Their tools are already propriatary.. they just don't realise it... try taking an ASIC design from one design house to another and see what the NRE cost is!

You will probably have to wait for someone ding a PhD thesis before it happens... sorry :-)

Synplicity Don't do placement.. not yet.. you can get Advantage or add ons (to bring the cost up to 100k of course) that can do some placement... but they optimise the code, put timing constraints in etc and rely on X or A to provide the final place and route.

Schematic design is old school... VHDL and Verilog are the two main languages taught... even the schematics I enter into Mentor's HDL designer are actually just converted into VHDL. I doupt if universities are even teaching schematic design or good practice.. I have seen some atrocious designs from a university graduate.

They are generally worse for documentation than the original design

Most places actually place using a random number generator.. most of the time it works but its not very optimal Xilinx used to (maybe still do) allow you to fix the seed so the sequance is always the same.

you forgot the key to business ... fast, quick, (mostly) working... so good enough is often all the accountants care about. If it does what's wanted then its out the door

Simon

But if they weren't accurate.. people would complain... and if they were.. then there's another slinging match between A & X marketing department over which is better / faster.... you really can't win.

Besides.. when it comes down to it.. A & X produce silicon.. not tools.. they aim for 90% of the users to be happy and the last 10% aren't worth the trouble. They can conform or X will read about the company in the chapter

I was once told that if you can sell a product to 1% of the American public.. you are a multi millionaire... so imagine 90% of hi-tech companies. When it comes down to it its all about money... most profit for the least amount of effort. The last 10% is always the most effort and least profitable... That is the bottom line of any business.

Simon

"What will happen is the ASIC guys will retrain or end up working at MacDonnalds..."

I hope thats just your humour, ASIC guys are streets ahead in HW design over most newbie FPGA guys, but we bring with us a higher set of expectations. ASIC guys will have to get used to slightly different style of HW design, and poorer tools. I suppose some of the ASIC EDA companies will follow on.

"Top down is a far better approact anyway.. at least the tools vendors will always tell you that.. and people leaning structured programming too.. bottom up will gradually become a forgotten aspect of design as the tools become good enough and the devices too fast. I have even put my OOP and strutured programming to work in my own designs... not as complex as Delphi OOP but same concepts apply. "

No no no. For average so so design top down is the quickest way out the door but it also leads one straight into hidden brick wall on performance.

Its only if you have the time to assemble bottom up that you can see where all the 0.1ns disappear that you have half a chance to get them back. Once you see that then iti possible to do top down and bottom up at the same time, but it does take longer.

Its the same difference between a 32bit cpu that works at 150MHz v another at 300MHz.

Top down and you automatically do 1 cycle, single threaded, looks like a DLX, type of design that is bottlenecked all over, no hope of ever speeding it up since control decisions can't be pipelined any further.

Bottom up and you look at how DSP is essentially thread driven (ie super pipelined) with as little control decision per clock as possible ie highest possible clock rate. You end up with multicycle multithreaded design instead that don't look anything like the text book cpu designs, not even any bigger either.

It will be interesting to see if ASIC guys change the FPGA business any, or the reverse.

Most FPGA designs I guess are bespoke projects. Most ASIC designs are the opposite, highest possible volumes and highest possible performance to have perf edge.

"you forgot the key to business ... fast, quick, (mostly) working... so good enough is often all the accountants care about. If it does what's wanted then its out the door "

Thats probably true in the FPGA biz, but its not like that in the ASIC side of things.

JJ

exactly my experience - especially with large FPGAs when most BRAMs (or presumeably other coarse-grain elements are used). once you fix position of those the rest seems to fall in place much easier. one can figure out what and where to fix after a few trial runs. and it seems to be more effective than constraining critical paths. dealing with LUT placement seems to be a mess - especially after havoc wreaked by synthesis tool optimizations ;o)

the problem is these trial runs/experience thing makes it black art- like. too bad noone bothered to write up the experiences gathered while trial running...

anyways, thansk to all for responses ;o)

lukasz

I'd like to add a reasonable pinout to that.

Before trying LUT placement, try register placement. Register names are more much stable. And again, with the registers correctly placed the rest can fall into place neatly.

To do LUT placement, the best way I've seen to do this is to prevent synthesis optimization by putting the logic for the LUT into an entity and putting the correct attribute on it. Then you can instantiate and place it with a generate loop in VHDL.

-- Phil Hays Phil-hays at posting domain (- .net + .com) should work for email

Being from the 'hey, I just got my Spartan 3 kit' subgroup, I can hardly boast 20+ years of battles with, well, anything. But so far I've been doing al my designing trough schematic entry, and seeing how it gets routed/placed has been quite surprising. And the thing I'm developping right now has very tight timing requirements so I end up placing all the important flip-flops by hand and wishing I could also control what kind of interconnect gets used.

Having studied the datasheet quite well before getting into this, it is a lot easier for me to map a desired circuit into FFs, LUTs and the like. Learning VHDL or even using the schematic editor, feels like a terribly involved way to convince the software to configure those LUTs the way I want them. So yes, I can imagine some demand for a FPGA layout tool that stays this close to the hardware. But 'realy slick and commercial' probably would put it out of my reach.

Regards, Paul Boven.

In same line though slightly off topic. are there still schematic based design being done (other than FSMs) and what tools do they use?

I'm not aware of any book that gives good explanation however I can suggest a simple solution.

Write a simple code and I do mean simple like 2 bit counter or something like this which you know how the logic should have been done if you had to draw it using gates and FF's.

Now synthesis and place and route it and open the floorplaner or fpga editor or even better both and see that you recognize what it what and so on.

Than try to move it to be where you want it to be and see what was added to the constrain editor (Once you move thing around you can ask the tool to save the needed constrain in the constrain file)

Look on the constrain file and see if it make sense to you.

Now come the fun part, try remove some of those constrain and see what happen. As you will notice some constrain are nice but not necessarily needed at least on many case while other do.

Now that you feel more comfortable make another simple design like maybe state machine with 2 bits or something else, synthesis place and route and see what you got. Than add constrain to put the FF for example where you want and than synthesis and place and route it and see if they moved to the place you ask them to move.

Only after you got comfortable with the small design go the your main design as in big design you have so much wiring going all over as well as less space to move thing not to mention when you move one thing you might be hurting something else and than need to fix another problem and before you know you will see that sometime to fix one problem you need to generate two new and fix them as well.

You might want also later to play with logic lock to tell the tool in what area to put your state machine and so on, but always try it first with small design where you can see what happen and not get "overwhelmed" due to other part which make it difficult to figure what it what and where until you get accustom.

Have fun.

PhD.

... its

are

not

Flooplanning is a lot of PCB layout, except instead of ICs you have lots of logic blocks. And if your design entry is an HDL, then oftentimes those logic blocks have arbitrary reference designators and netnames, which makes correlating the logic to its function rather difficult.

Anyways, my point is that PhDs don't do PCB layout. Having seen the results of a PhD's layout, there's a real good reason for that!

As others have said, layout is a visual process that requires a knack. You've either got it or not.

(Cue: "My Sharona")

-a

LUTs

have

The Guys at HierDesign thought so. They came up with a product called "PlanAhead" which now belongs to Xilinx. see:

or