I have a system composed of a Cyclone device and an8051-like CPU, which acts as a passive-serial configuration device and later as a USB2.0 coupler. The FPGA configuration image is clocked to Cyclone using the UART interface (synchronous mode 0, i.e. TXD acts as DCLK and RXD presents one bit at a time to the DATA0 pin). There are also two inverters at these lines: the first one inverts DCLK, because Cyclone uses the opposite edge than '51 to latch a configuration bit. The second inverter (at RXD -> DATA0) relaxes timing constraints by compensating the delay introduced by DCLK inversion.
Now I would like to reuse resources and add a serial synchronous communication channel between Cyclone and '51, where Cyclone acts as a slave device. So, is it possible to read DCLK and DATA0 from an operating Cyclone, i.e. to simulate an ASMI-like interface?
Best regards Piotr Wyderski