SPI interface cpol & cpha

Hi Praveen,

Right, if you control both the master and the slave you need only one format, I'd suggest the default cpol = cpha = 0. However some of us are not so lucky and must interface with pre-existing real world devices which, through the perversity of history, can be hard-wired for any of the four formats. No use saying it doesn't need to be so, it simply is so. The fun begins when you have a mixture of devices using different cpol & cpha values.

hth, Alf

Hi,

Any particular reason for suggesting cpol=cpha= '0'.

In some of the docs i have read that cpha='1' is generally suited for single master single slave applications , i am not able to figure out why?? Any comments on this!!

Thanks in advance, Praveen

Because is more likely to came across a chip with this configuration. Aurash

It's common.

Not really. To me either seems equally suited. Do these docs suggest that cpha='0' is somehow less suited or are you reading that into them?

Most simple logic ICs are sensitive to the raising clock edge. If you want to read a TTL shift register, data changes on the rising clock edge so you better sample on the falling one. Thus cpha=1.

Regards,

Iwo

The main difference is in whether you sample on negedge or posedge and similar for the other side.

For low frequency (100M or lower) you can almost always simple choose the mode where both side transmit on the negedge and sample on the posedge (or vice versa).

While this can help setup/hold issue this has the disadvantage of using only half of the period.

Therefore on higher frequency system were you can't pass the information in half period you will need both side to transmit on (the same edge e.g) posedge and sample on the posedge and if you have setup/hold issue take care of them in other ways.

Have fun.