Quartus II Fitter Problem


I have been using Altera Quartus II v4.2 SP1 for quite a long time. Recently, I have a problem that the fiiter change the logic equation compare to the synthesis.

  1. I wonder why the fitter need to change the post-synthesis logic equation during fitter stage.

More interesting is that the changes make my synchronous register behave asynchronously.

Post-synthesis logic equation : ZD1_RD_PTR[1] = DFFEAS(ZD1_RD_PTR[0], H1_rd_fifo_rd_clk, !PIN_RSTN, , , , , , );

Post-fitter logic equation : ZD1_RD_PTR[1] = DFFEAS( , GLOBAL(H1L39), !PIN_RSTN, , , ZD1_RD_PTR[0], , , VCC);

Obviously, the behaviour will totally different!

  1. Can someone tell me how to turn off the fitter optimization?


Reply to
Robert Au
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What is your design flow ? Do you use internal synthesis or third party tool ? Did you activate retiming (physical synthesis) ?

QII physical synthesis can now perform very clever optimizations, which often alter the local behavior but (hopefully!) respects the macroscopic behavior. Register retiming is such a well-know optimization technique.

In doubt, run a post-layout simulation to be sure. If it works, you shouldn't be worried by what the tool did to improve the design performance. If you worry (or if you somehow need to preserve the conformance between RTL and post-layout, like for formal verification purpose, or if you debug it at internal register level -STP II-), then you should disable physical synthesis.

The section is "Synthesis netlist optimization".

Bert Cuzeau

Reply to

Hi Robert,

Question 1: The two functions you list are equivalent. The first uses the D port of the register to bring in the registered data. The second uses the "synchronous load/asynchronous load data" port of the register to bring in the data, and sets sload = vcc so the data always comes through this port (never through D). This is done by the fitter automatically when it benefits timing or routability.

Question 2: There isn't any user-visible way to turn this optimization off, but it's perfectly safe so there's no reason to turn it off either.

Bert, this transoformation is not tied to physical synthesis -- this is a transformation that is purely structural and the fitter is always free to make it. You are defininitely correct that physical synthesis can make changes to the synthesis output when it is enabled though.


Vaughn Betz Altera [v b e t z (at) altera.com]

Reply to
Vaughn Betz

One slight clarification: it isn't impossible to turn off the optimization I list below, but it is a bit painful. Just in case you want to experiment though:

You can write routing constraints to force a certain port to be used on a block, such as the D-input to the FF, rather than the sync_data input. The entire Quartus router can be controlled on some or all signal nets by a routing language we call .rcf. You can write constraints that say "use any routing for this net, but you have to end on the data D port of this register." You can write pretty much any other constraint you can think of too.

See "Understanding the .rcf file" in the Quartus help for a description of the file format and how to use it to control the router. Normally it is only very advanced users who go to this level of control for highly performance critical parts of a design, or who need perfectly delay balanced routing for a custom source synchronous interface or some such, though.


Vaughn Altera [v b e t z (at) altera.com]

Reply to
Vaughn Betz

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