I have been using Altera Quartus II v4.2 SP1 for quite a long time. Recently, I have a problem that the fiiter change the logic equation compare to the synthesis.
- I wonder why the fitter need to change the post-synthesis logic equation during fitter stage.
More interesting is that the changes make my synchronous register behave asynchronously.
Post-synthesis logic equation : ZD1_RD_PTR = DFFEAS(ZD1_RD_PTR, H1_rd_fifo_rd_clk, !PIN_RSTN, , , , , , );
Post-fitter logic equation : ZD1_RD_PTR = DFFEAS( , GLOBAL(H1L39), !PIN_RSTN, , , ZD1_RD_PTR, , , VCC);
Obviously, the behaviour will totally different!
- Can someone tell me how to turn off the fitter optimization?