I remember a few years ago we would have to run ISE PAR several times in order to meet timing. One we had a decent layout, we would lock it down because of the chance of never being able to reproduce it.
Does ISE still suffer nondeterministic placement?
Also, how much has ISE PAR improved since 5.1/6.1?
-Tom
it
Howdy Tom,
I wouldn't call it nondeterministic. To me, non-deterministic means that if you give a single version the EXACT same input two times in a row, you might get a different output. I don't believe that has been the case for a while now.
What DOES happen is that if you change even the slightest thing, the synthesis tools (and therefore MAP and PAR) can take a VERY different "path" to implementing, mapping, and placing the design. Each is dependant on the previous step - so I think of it like the butterfly effect - a small (almost insignificant) change at the input can make huge changes at the output.
That behavior most definitely does still exist - but the only suffering going on is on the part of you and I :-)
I'll take a stab since noone else has. The last huge improvement that I noticed was the -timing option for MAP, which I thought was introduced (or at least revamped) in 6.x.
Other than that, I'm sure their algorithms have improved in general, but I've heard WAY too many cases, both on c.a.f and outside, of people re-running with newer versions tools and getting considerably different results (either it not fitting, or timing being off by a mile, or new errors, or in our case, the default I/O bank type changed). Even on dot releases, like between 6.1 and 6.3.
Lastly, higher speed and/or density designs in the older families (Virtex, Virtex-E, Spartan-II and Spartan-IIE), 6.3 is probably what you want:
Marc
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