Hello eveyone,
I have a design involving a Lattice ispMACH4384. The pinout is already fixed. I have to make a 5:1 24bit MUX. Unfortunately, the output pins are all located in GLB H, J and K. As the expert clearly sees, the 24bit MUX overloads the input signal capabilities of the GLBs (36 max.). So I want to split up the MUX into two cascaded MUXes. I tried the VHDL attribute syn_keep, but this is ignored by the fitter tools. How can I prevent the node collapsing for this 2 MUXes? Iam using ispLEVER with Synplify.
Regards Falk