CPLD Fitting problem

Falk Brunner schrieb:

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Why do you want to use the KEEP attribute at all ? What does the fitter do you want to prevent, why do you want to prevent that? Some code?

Rgds Andr=E9

If you have a spare i/o pin attach the intermediate mux o/p to that. It is a dirty trick but usually works. I used to do something like this in the old days with Intel (later Altera) flexlogic which had a 24V10 structure and forever was running out of block fan-in signals. I don't often see problem now with the CPLDs I tend to use.

Similar vein - if you can register an intermediary o/p then you can get the same result. You can use opposite clock edges if your design uses a clocked o/p and the device supports if you want to avoid an extra clock latency.

You can also look at synthesiser switches but I'm slightly rusty of Synplify to tell you exactly the switches.

Taking some of the logic to files lower in your structure and ensuring no boundry optimisation can work as well.

You can also instantiate components such as final OR for the intermediate term may also give the desired result.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.

Thanks for the valuable hints. I registered the second MUX on the falling edge and everything is fine. Quick'n'dirty. ;-)

Regards Falk