Field-Programmable Gate Arrays

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Chipscope and LVDS clock (IBUFGDS)

Hello, i am working with chipscope pro 7.1 with following code: entity BoardTest is Port( led_o : out std_logic_vector(...
0 comments posted 21yrs
posted by Nightstorm
0 comments posted 21yrs posted by Nightstorm

why can't i use opb_spi core in EDK6.3?

I have added the opb_spi core in my project,I can assure the opb_spi have been inserted in the project(because i can fi...
5 comments posted 21yrs
posted by mlpei279
5 comments posted 21yrs posted by mlpei279

Query -V2Pro fpga programming

Hello , I have the following questions regarding the FPGA programming: I have generated the bit stream file from the ve...
1 comments posted 21yrs
posted by nkishorebabu123
1 comments posted 21yrs posted by nkishorebabu123

Anybody know cost/supplier for Virtex-4 LX40?

Hi All, It seems impossible to get prices out of some electronic parts vendors ! Does anybody now a supplier or the pric...
0 comments posted 21yrs
posted by andyesquire
0 comments posted 21yrs posted by andyesquire

Spartan 3 kit FPGA configuration problem

I can program the platform flash OK on my Spartan 3 kit using the parallel cable and the application runs OK, but I can...
2 comments posted 21yrs
posted by leon.heller
2 comments posted 21yrs posted by leon.heller

How to speed up float computing

Hi all, I am doing some programmes with EDK 6.3i on the Virtex-II Pro50. There are many math computing in the program,...
5 comments posted 21yrs
posted by lnzhao
5 comments posted 21yrs posted by lnzhao

problems with Ultra DMA operations with ATA HDD

Hi there! I have the following problem. I develop FPGA IP core for ATA HDD. I have tested it on 40 GB 2.5" Fujitsu HDD....
2 comments posted 21yrs
posted by Eug
2 comments posted 21yrs posted by Eug

need a book: Hilbert transform

Hi, Can anybody recommend a book that has good stuff about implementing the discrete Hilbert transform, preferably in a...
19 comments posted 21yrs
posted by jjlarkin
19 comments posted 21yrs posted by jjlarkin

Implementing sin function in fpga

I am attempting to implement a sine function using cordic method. I can't figure out how to reduce an arbitrary angle t...
9 comments posted 21yrs
posted by pvnguyen
9 comments posted 21yrs posted by pvnguyen

regional clk to dcm? possible or not?

Hey, I have to start a V4 design and am looking through a datasheet and i was wondering if you can connect a regional c...
1 comments posted 21yrs
posted by Yttrium
1 comments posted 21yrs posted by Yttrium

How fast multiplier in VirtexE?

I am using CoreGen Multiplier (target Virtex-300E speed -7), I have strugled to make it runs at about 6.5ns, and that's...
0 comments posted 21yrs
posted by ccon67
0 comments posted 21yrs posted by ccon67

Altera NIOS2 50.0 SOPC periphals broken???

Trying to run some small system with NIOS2 and timer/uart periphal... 1. Problem...regardless what I set for the UART a...
3 comments posted 21yrs
posted by me
3 comments posted 21yrs posted by me

Xilinx DDR output registers

There's been a little side discussion about the Xilinx IOB cell DDR output registers. The common idea of a DDR output r...
5 comments posted 21yrs
posted by johnhandwork
5 comments posted 21yrs posted by johnhandwork

JTAG Programming Problem

Hi, I am trying to implement the PCI Brige in a Spartan II board (XC2S200). The problem is when I try to program the bo...
3 comments posted 21yrs
posted by jorgetrabal
3 comments posted 21yrs posted by jorgetrabal