Hello,
i am working with chipscope pro 7.1 with following code:
entity BoardTest is Port( led_o : out std_logic_vector(3 downto 0); clk_prg_p_i : in std_logic; clk_prg_n_i : in std_logic); end BoardTest;
attribute IOSTANDARD : string ; attribute BOX_TYPE : string ;
component IBUFGDS port ( I : in std_logic; IB : in std_logic; O : out std_logic); end component;
attribute IOSTANDARD of IBUFGDS : component is "LVDS_25"; attribute BOX_TYPE of IBUFGDS : component is "BLACK_BOX";
begin
U1: IBUFGDS port map (I => clk_prg_p_i, IB => clk_prg_n_i, O =>
clk_prg_i);
A: process (clk_prg_i, res) begin if res = '1' then counter_a '0'); elsif clk_prg_i = '1' and clk_prg_i'event then counter_a