Field-Programmable Gate Arrays

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Viewing internal signal in Modelsim (post P&R)

Hi all, I am using ModelSim PE 6.0d. I have done functional simulation for my design (i could view all internal signals...
3 comments posted 21yrs
posted by Puneetsingh81
3 comments posted 21yrs posted by Puneetsingh81

Adding Verilog processing core to Viretx2Pro at ML310

Hi, I have a Verilog processing core. I want to implement it on Vertex2Pro device as a separate core , adding it to cur...
3 comments posted 21yrs
posted by sanjaypratapsingh
3 comments posted 21yrs posted by sanjaypratapsingh

never seen XST error

what about this error? --------------------------------- INTERNAL_ERROR:Xst:cmain.c:3022:1.146.4.1 - To resolve this er...
3 comments posted 21yrs
posted by john.wo.71
3 comments posted 21yrs posted by john.wo.71

RAM State Machine Examples

Hallo, I have made some searches with google, but I don't have found anything. There is someone who could tell me about...
2 comments posted 21yrs
posted by marcotoschi_no_spam
2 comments posted 21yrs posted by marcotoschi_no_spam

Xilinx LVDS and SCSI

Hi, I want to implement a SCSI Ultra-160 or SCSI Ultra-320 host on a VirtexII-Pro FPGA. My goal is to connect the FPGA...
1 comments posted 21yrs
posted by lucas_bossetti
1 comments posted 21yrs posted by lucas_bossetti

trouble trying to debug c code on MicroBlaze

At the date :2005-06-10 06:37:51 I sendt out a message with the subject: A lot of trouble when trying to debug c code o...
4 comments posted 21yrs
posted by raybakk
4 comments posted 21yrs posted by raybakk

Suche FPGA Protoboard

Hallo, ich bin auf der Suche nach einem g=FCnstigen FPGA-Prototyping Board. es sollte auf einem Altera Cyclone bzw. Cyc...
1 comments posted 21yrs
posted by Harald.Obereder
1 comments posted 21yrs posted by Harald.Obereder

Pb with an IPCore Dual Port Memory

Hi, I had problems implementing an IPCore "Dual Port Memory" in a new block of my code. It seems that the instanciation...
0 comments posted 21yrs
posted by pistre
0 comments posted 21yrs posted by pistre

Searching FPGA board for private use

Hello, I came in contact with FPGAs at the university and have done some designs. Now I decided to start with FPGAs in...
8 comments posted 21yrs
posted by michaeldre
8 comments posted 21yrs posted by michaeldre

xilinx ml310 : to run applications on 2 nd ppc

Hi , I have build an system with 2 ppc 405 and I want to run application programs on 2 nd ppc but not on 1 st, I dont k...
1 comments posted 21yrs
posted by jagadeeshreddy_s
1 comments posted 21yrs posted by jagadeeshreddy_s

How to pipeline Loop Logic?

Hi all, It's intuitive to pipeline a feed-forward combinational logic. But how to pipeline the Loop without changing th...
1 comments posted 21yrs
posted by zhushenli
1 comments posted 21yrs posted by zhushenli

OrCAD Symbol For Xilinx V2PRO

Hello! Does anyone know where I can get the symbol for an XC2VP30-FF896 part? I use OrCAD. Many thanks, Robert
9 comments posted 21yrs
posted by robnstef
9 comments posted 21yrs posted by robnstef

Best Practices for Hardware Designers

Hello, I'm looking for some information that describes some of the best practices or habits for successful electronic d...
14 comments posted 21yrs
posted by jjlindula
14 comments posted 21yrs posted by jjlindula

Synplify vs XST...

I have not use XST, but it is becoming more attractive. I have been using Synplify for many years now, and it works pre...
11 comments posted 21yrs
posted by austin
11 comments posted 21yrs posted by austin