Field-Programmable Gate Arrays

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ModelSim Timing Simulation Signal Names

First time post... Quick question regarding post PAR simulation. What can be done to retain sensible signal names when...
7 comments posted 21yrs
posted by peter
7 comments posted 21yrs posted by peter

Xilinx: XST synchronous FIFO using BRAMs

Dear all, Lately I have been trying to design and implement a synchronous FIFO using a cyclic buffer, that can be synth...
26 comments posted 21yrs
posted by sidney
26 comments posted 21yrs posted by sidney

FPGA system RAM

I am in the early design stages of an FPGA-based audio / video stream source and sink. The FPGA board will be an ethern...
5 comments posted 21yrs
posted by dougdjones
5 comments posted 21yrs posted by dougdjones

Foundation 3.1 in WinXP machine Problems!

Hi, I have tried today to install Foundation 3.1 in my windows xp machine. I have not done any FPGA design for 4 years...
4 comments posted 21yrs
posted by nicemanYep
4 comments posted 21yrs posted by nicemanYep

vhdl source code cross reference tool

Is anyone aware of a software package that can cross reference vhdl language components and instantiations of those com...
2 comments posted 21yrs
posted by wallge
2 comments posted 21yrs posted by wallge

interpolation in FPGA

Hello! I like to know if anybody have done any interpolation (e.g quadrature) in FPGA or where I can get application no...
3 comments posted 21yrs
posted by sinebrate
3 comments posted 21yrs posted by sinebrate

Avnet V4 - XC4VLX25

Could somebody help me about this board? My company bought this Evaluation Kit and in User Guide in user information wr...
1 comments posted 21yrs
posted by diod2003
1 comments posted 21yrs posted by diod2003

Cyclone Board with // LVDS lines

Hi! I've already googled and dug through several online lists of FPGA boards, but haven't found what I'm looking for, y...
1 comments posted 21yrs
posted by e_s_p_i_a_n_
1 comments posted 21yrs posted by e_s_p_i_a_n_

Direct audio output from FPGA pins

I'm playing around with sigma-delat ADC and DAC for audio. It's amazing how good this works without any active componen...
9 comments posted 21yrs
posted by mschoebe
9 comments posted 21yrs posted by mschoebe

LogiCore: SGMII autonegotiation

All, I have instatiated the SGMII block into my design and am attempting to get it to autonegotiate. It sends out the /...
0 comments posted 21yrs
posted by tom.brooks
0 comments posted 21yrs posted by tom.brooks

Avnet V2P development kit woes

Has anyone used avnet's V2P development kit? if so maybe you could help with some questions i've been struggling with....
1 comments posted 21yrs
posted by wallge
1 comments posted 21yrs posted by wallge

FPGA development board - urgently

Does anybody know where I can buy FPGA PC104 development board with FPGA that have embedded PLL, syncronius 32Megabit (...
1 comments posted 21yrs
posted by sinebrate
1 comments posted 21yrs posted by sinebrate

aurora framing

All Does anyone know whether with aurora framing mode you HAVE to assert end_of_frame ever (I can see why you might wan...
1 comments posted 21yrs
posted by weston_katherine
1 comments posted 21yrs posted by weston_katherine

Coverting .mcs file to .bit file

Hello, Is there any way of converting an .mcs file into a bit file....in Xilinx FPGAs Any help would be greatly apprecia...
3 comments posted 21yrs
posted by shailesh.radhakrishnan
3 comments posted 21yrs posted by shailesh.radhakrishnan

ip core supply

plz touch me more detail if u need the following ip. brahms snipped-for-privacy@yahoo.it ******************************...
3 comments posted 21yrs
posted by brahms_view
3 comments posted 21yrs posted by brahms_view