Stratix open-drain pins

Hi,

Anyone know if I can configure the output pins of a Stratix FPGA to be open-drain?

I need open-drain outputs to interface with an SMBus slave device.

Thanks, Ernie

I'm no expert in stratix but I guess you can model the output buffer with :

OE ------, |\_____ Out IN ----|/

Just tie IN to GND and use OE as you command signal.

my_od_out

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Yes, the Stratix device can. You can also put a weak-pull up on the = output pin if you wish.

Open-Drain Output

Stratix devices provide an optional open-drain (equivalent to an = opencollector)

output for each I/O pin. This open-drain output enables the

device to provide system-level control signals (e.g., interrupt and = writeenable

signals) that can be asserted by any of several devices.

=20

Thanks Rob.

How do I tell Quartus that I want a specific pin to be open drain? Do I have to do something special? Or is it automatic and transparent to the user?

Thanks, Ernie

It will be inferred automatically from the code if you write it as Sylvain suggested.

my_od_out

Thanks Mike,

That helps a lot. I appreciate it!

Cheers, Ernie