Field-Programmable Gate Arrays

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Unrolled Pipeline Implementation

Hi Guys, I am writing some verilog to implement an unrolled pipeline for a vector mode cordic function. What I end up h...
3 comments posted 21yrs
posted by psolomon
3 comments posted 21yrs posted by psolomon

QII simulation annoyance

Many of the nodes I want to probe seem unavailable in the simulation. They are either optimized away, or refuse to show...
13 comments posted 21yrs
posted by tns1
13 comments posted 21yrs posted by tns1

Testbenching and verification

Hi All, I am using Quartus and I have acess to Modelsim, and I have been working on a project that is RF based containi...
3 comments posted 21yrs
posted by psolomon
3 comments posted 21yrs posted by psolomon

output-value isn't stored

I want to build an easy decode-logic in VHDL. My problem is that the value I write to the output isn't stored till it s...
4 comments posted 21yrs
posted by manfred.balik
4 comments posted 21yrs posted by manfred.balik

stupid question about XPS peripheral filenames

Why are all the data files of the peripherals all postfixed with v2_1_0? At first I thought it was a version number, bu...
1 comments posted 21yrs
posted by zoinks
1 comments posted 21yrs posted by zoinks

Wishbone RTL simulator

Hi all, does anybody know if a rtl simulator of the wishbone bus exist and, in case it does, if it is available somewhe...
3 comments posted 21yrs
posted by sabatian
3 comments posted 21yrs posted by sabatian

Search for FPGA

Hello, I'm looking for a small FPGA which needs only one voltage source and has about 10 kByte internal RAM.Since we ha...
6 comments posted 21yrs
posted by Thomas.Reinemann
6 comments posted 21yrs posted by Thomas.Reinemann

Quartus Timing Issues

Hi Guys, I am a relatively inexperienced user of Quartus (I did a thesis on it and now I am mucking around trying to ge...
3 comments posted 21yrs
posted by psolomon
3 comments posted 21yrs posted by psolomon

design does not fit in device

Hi. I have a design target to xilinx virtex2pro30 device. In the map stage I get "ERROR:342 design does not fit in devi...
3 comments posted 21yrs
posted by nahum_barnea
3 comments posted 21yrs posted by nahum_barnea

Altera QII WE Tutorials

Looking for some help/advice in using Altera QII-WE. I am an electronics student working with MSI & SSI 7400LS chip set...
2 comments posted 21yrs
posted by d_tonkes
2 comments posted 21yrs posted by d_tonkes

Rocket IO failure after power cycle.

In the system I work on, we use Rocket IO to communication between the different boards. I see some Rocket IO failures...
2 comments posted 21yrs
posted by tony.p.lee
2 comments posted 21yrs posted by tony.p.lee

Announce: Impulse C-to-RTL Version 2 now available

[Commercial announcement follows] Impulse CoDeveloper is a C-to-RTL tool targeting FPGAs and FPGA-based hardware/softwa...
6 comments posted 21yrs
posted by dpellerin
6 comments posted 21yrs posted by dpellerin