Hi Guys,
I am writing some verilog to implement an unrolled pipeline for a vector mode cordic function.
What I end up having is a bunch of repeating statements with slight differences, such as..
if (y[3] > 0) begin x[4]
Use hierarchy. Create a parameterized component that is one iteration, with the iteration number being a parameter, then in the next level up you instantiate these components. This is one of those instances where VHDL is easier than Verilog. With VHDL, you use a generate statement to instantiate as many of the interation components as you need. The generate loop index gets plugged right into the iteration number generic for the iteration component and viola, an unrolled CORDIC processor that is parameterized for the number of iterations. Verilog 2000 has a generate capability, but it is a little awkward passing the generate index as a parameter into a sub-module like that, especially if you are also doing placement in the code.
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Verilog 2001 allows generate loops for just this sort of purpose. The genvar variable in the loop can be used for indexing, selecting +/- and generating the constant. Look up the generate "for" loop in your synthesis (or simulation) tool reference.
needs
Sure, yes, do it in VHDL! :) The fun part asides, you can only do it in Verilog 2001 (yet I find the VHDL way more elegant) but be sure to check your toolset as not all of them support Verilog 2001, yet.
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