Latest threads in Field-Programmable Gate Arrays

Ethernet reference design for ML310?

Is there a simple tutorial or reference design available that implements the ethernet IP from Xilinx? I have stepped th...

3 21yrs

joeylrios

3 21yrs joeylrios

Xilinx ISE 7.1 : Macro search path in Transalate

Hi Is it possible to set a relative path into in translate properties (ngdbuild) ? I tried it on 7.1 and doesn't work. B...

1 21yrs

pierrotlafouine

1 21yrs pierrotlafouine

Timespec for DCM outputs (Spartan 3) ?

Hi everyone, I'm using all the four phase-out signals from a DCM (0, 90, 180 and 270 degrees offset) to each clock a si...

7 21yrs

p.boven

7 21yrs p.boven

Running prog from PROM

Hi, I would like to know how we can store a program in the on-board PROMs. My CORE takes up 36 out of the 44 available...

7 21yrs

johnsons

7 21yrs johnsons

Possible bug in Vertex-4 Rocket-IO?

I need to use Rocket-IO in Vertex-4 to receive data at the rate of 6.22Gbps. My reference clock input to the Rocket-IO...

9 21yrs

shuo.huang

9 21yrs shuo.huang

Xilinx V2Pro reconfiguration

Hi, I'm a student from germany and try to develop a dynamic reconfiguration application for a virtex-2 pro fpga. The ap...

0 21yrs

sven-habermann

0 21yrs sven-habermann

Ray Andraka when will your book be on store???

Hello Mr.Ray Andraka, I have heard that you are written a book on "DSP on FPGA". Please let me know when it is schedule...

3 21yrs

stud_lang_jap

3 21yrs stud_lang_jap

Stacked Die devices

>>>> Imagine a stacked die FPGA, with a large VFast SRAM, and Config device ? >>> >>> Uwe B >>> You're dreaming >> >> >...

0 21yrs

no.spam

0 21yrs no.spam

Verilog exponential operator issues in simulation (ISE 7.1 SP3 w/ ModelSim 6.0a)

Hi, I'm using the Verilog-2001 exponential operator to do the following: `define NUM_COUNTER_BITS 8; parameter NUM_COUN...

6 21yrs

njoroge

6 21yrs njoroge

Resampling in FPGA with irrational or large rational ratios

Resampling with small integer ratios can be pretty staightforward, like a rate change of 3/2, upsample by 3 -> LPF -> d...

1 21yrs

bgaughan

1 21yrs bgaughan

Max Sample Rate for Signal Tap in Altera Quartus?

Hello, does anyone know what is the max Sample Rate used in the Signal Tap utility under Altera's Quartus? Thanks, joe

5 21yrs

jjlindula

5 21yrs jjlindula

Verilog Coding Guidelines

Hello All, I spent few weeks researching different books and my experience in verilog to write this detailed article. H...

1 21yrs

pistony2k

1 21yrs pistony2k

QAM 64 implementation on a FPGA board

Hi all, We are trying to implement QAM 64 modulation on a 1Gbps signal to fit in a 200MHz bandwidth using FPGA's. We ar...

0 21yrs

fidodido93

0 21yrs fidodido93

Bit serial, book, other info???

Hello I?m looking for some good book about bit serial programming. I?m interested in learning about it to implement fun...

4 21yrs

blabla

4 21yrs blabla

aurora reliability

All Does anyone have a feel for how robust aurora is? I have worked out a packet based protocol to put on top of aurora...

5 21yrs

weston_katherine

5 21yrs weston_katherine

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