Wishbone RTL simulator

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Hi all,

does anybody know if a rtl simulator of the wishbone bus exist and, in
case it does, if it is available somewhere? I looked on the opencores
website but i did not fined anything about it.

Thanks in advance,


Re: Wishbone RTL simulator
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there are simulators for RTL and testbenches for the Wishbone, there is no
such thing as 'wishbone simulator' you just run your HDL simulator on the
wishbone testbench thats it.


Re: Wishbone RTL simulator

you are right. i wrote the message too fast and my point was not clear
at all. what i wanted to ask was the following: i could probably be
asked to design an fpga module in order to be wishbone compliant and i
wanted to know if somewhere some vhdl procedures, functions, packages
or whatever emulating the wishbone timing were available to test my
wishbone interface. i am still searching the web but i did not find
anything like this yet.



Re: Wishbone RTL simulator

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There are several wishbone master and slave modules floating
around on opencores. You can use those to validate your

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Rudolf Usselmann,  ASICS World Services,  http://www.asics.ws
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