Wishbone RTL simulator

"hata" schrieb im Newsbeitrag news: snipped-for-privacy@g44g2000cwa.googlegroups.com...

there are simulators for RTL and testbenches for the Wishbone, there is no such thing as 'wishbone simulator' you just run your HDL simulator on the wishbone testbench thats it.

Antti

antti,

you are right. i wrote the message too fast and my point was not clear at all. what i wanted to ask was the following: i could probably be asked to design an fpga module in order to be wishbone compliant and i wanted to know if somewhere some vhdl procedures, functions, packages or whatever emulating the wishbone timing were available to test my wishbone interface. i am still searching the web but i did not find anything like this yet.

regards,

hata

There are several wishbone master and slave modules floating around on opencores. You can use those to validate your implementation.

Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services,