Implement a JTAG controller in an FPGA

Anyone done a JTAG controller in VHDL or Verilog?

I want to use an FPGA to program another JTAG device.

Cheers,

Irish

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irish
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As far as I remember, Lattice has a reference design on multiple boundary scan port linker, see

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I think this can be used to program other devices through one centralised device. Please correct me if I'm wrong.

Luc

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Luc

"Luc" schrieb im Newsbeitrag news: snipped-for-privacy@4ax.com...

there are only JEDEC files for the those boundary scan linker designs, not much useful at all

and I think OP was not looking for this type of thing but TAP master

Antti

Reply to
Antti Lukats

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