Clock recovery in FPGA at 300 MHZ

Hi all,

I want to implement a clock extraction circuit from data at 300 Mbps. What i wanted to know is that is it really feasible in FPGA's( CYCLONE II).

Is any reference design available on clock extraction circiuit.

Thanks in advance

Regards, Praveen

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Hi praveen,

Altera has two reference designs for Cyclone I that do clock/data recovery at 270MHz for DVB/ASI and SDI. It may be possible to crank this up to

300MHz when using the fastest speed grade Cyclone but it's going to be tricky.

Best regards,


Reply to
Ben Twijnstra

Cyclone II is faster than Cyclone I, so if this is hitting 270 MHz in Cyclone I, there's a pretty good chance it'll run at 300 MHz in Cyclone II. But of course, the speed-up from Cyclone I to Cyclone II is circuit dependent, so I can't say that for sure for this particular circuit you'll get the speed boost you need -- you'll need to try and see.


Vaughn Altera [v b e t z (at)]

Reply to
Vaughn Betz

Hi Ben,

Can you give me the po> Hi praveen,

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