Xilinx Conversion 3.1 --> 6.1

Max,

Unfortunately your old schematic is in a proprietary Aldec format. Xilinx no longer uses Aldec for their ISE environment.

You have few options.

1. If you just need to update and build the old project for the original parts (that were supported in version 3.1) the best bet is to continue to use 3.1 - I am using 4.1 (the last of the Aldec-based versions) on the same machine with 6.1 and all I need to do is change my Xilinx environment variable to switch between modes.

1. Use the export option in version 3.1 schematics to generate structural VHDL code from your old schematic. This code will of course lose your graphics and text comments, but with some coercing can be made to compile under ISE (you may need to add some library elements that are no longer in unisims). It may actually be less work to re-create the schematics by hand.

2. Hand Aldec a pile of m> Hi all,

I have not done it for a while but if you have the 3.1 tools I think you can export the design to VHDL. It isn't friendly as you basically get a vhdl netlist style output but it does allow then to take the output into the new tools.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.

Thank's for your repaly

The problem is that the PC with 3.1 crash and i can't find installation CD :-( I've only me project files and the version 6.1

Could you help me?

Thank's

Max

udicom

Max,

It seems your best bet is to try the Aldec approach. They can get you started with an evaluation license (I think it's good for 1 month) and they have some app notes on migrating your old designs from Xilinx Foundation. If you don't keep the tools after the eval, you'll still have had a chance to look at and print your old schematics and possibly convert them into something usable by the 6.1 tools. If nothing else the Aldec tools should still have the VHDL export option.

Good luck, Gabor

Max wrote: [Snip]

What about the old archived versions of webpack ?