Field-Programmable Gate Arrays

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Asynchronous Priority comparator

+HI, Is it possible to create a comparator structure that has a priority structure eg My system has more than 65% cases...
3 comments posted 21yrs
posted by llabakdas
3 comments posted 21yrs posted by llabakdas

chipscope on opb bus

Hello, i'm using XPS to build a system based on a Microblaze cpu, and i would like to add a Chipscope OPB IBA to analys...
1 comments posted 21yrs
posted by bazogec
1 comments posted 21yrs posted by bazogec

Confused with "task" keyword.

I wrote a task to feed test vectors to my design, however, I realized some differences between "task" and the normal st...
0 comments posted 21yrs
posted by F.r.a.n.c.i.s.C.h.e.e.(Remove the dots)
0 comments posted 21yrs posted by F.r.a.n.c.i.s.C.h.e.e.(Remove the dots)

comprehension of clck to pad,clock to setup,etc

Hi, I want to understand the basic path types as: clock t osetu; clock to pad because i have many problems when i made...
1 comments posted 21yrs
posted by lnadjwa
1 comments posted 21yrs posted by lnadjwa

Distributed Arithmetic Architecture - LUT Contents

I am trying understand how a distributed arithmetic design can achieve a density of 1 LUT(4 input) per four taps per in...
1 comments posted 21yrs
posted by andrew.newsgroup
1 comments posted 21yrs posted by andrew.newsgroup

Virtex4 local clock timing

Has anyone seen any timing specs for the V4 local/regional clocks? I don't see anything in the data sheets. I'm interes...
2 comments posted 21yrs
posted by johnp3+nospam
2 comments posted 21yrs posted by johnp3+nospam

Virtex 2 Pro Routing Constraints

Is there any contrainsts for the V2P to disallow routing in a certain area?
2 comments posted 21yrs
posted by Hua.Zheng
2 comments posted 21yrs posted by Hua.Zheng

Free 8 bit micro for fpga

Just saw that Lattice announced a free open source 8 bit micro on their site. http://www.latticesemi.com/products/devto...
8 comments posted 21yrs
posted by themarenas
8 comments posted 21yrs posted by themarenas

How to implement Evolvable Hardware ?

Hello Everyone I am a final year student pursuing my undergraduate research project on the topic of "Evolvable Hardware...
0 comments posted 21yrs
posted by apsolar
0 comments posted 21yrs posted by apsolar

Exact time-to-Failure data for FPGA devices

Hi All, I was wondering if somebody knows where to find exact time-to-failure data for FPGA devices. I checked the reli...
6 comments posted 21yrs
posted by amrahmadain
6 comments posted 21yrs posted by amrahmadain

How to look inside a RAM memory

Hello everybody, I use FPGA Advantage 6.2 and ISE Xilinx 7.1. Is there some tool that allows for the verification of th...
3 comments posted 21yrs
posted by giovanniparodi79
3 comments posted 21yrs posted by giovanniparodi79

Excalibur full strip simulation on solaris.

Can anybody help me to run full strip simualtion on my excalibur epxa4-1020(embeded arm 9 device) ? . i followed the in...
2 comments posted 21yrs
posted by aries
2 comments posted 21yrs posted by aries