As Peter says, there is no "wear out" mechanism at work, so we are talking about a latent defect that finally results in a junction failure, or a gate rupture, or a mechanical failure of the connections (solder bump cracking, package via opening, printed circuit board wiring breaking).
The HTOL data is available from our Reliability group through our FAEs to users who wish to examine it (under NDA).
Basically here you will see the equations, the tests at elevated temperatures, and any failures that have occured, and what and where they were (and what changes were made to improve the product as a result).
For example, I have ~ 6,000 devices running 24X7 for the Rosetta experiments, and I have not had a single failure in ~ 300 gigabit-years (take the number of bits in a device, and multiply by years, and divide by 1E9 to get Gb-yrs). So normal operation will never predict a FIT rate (just takes to long to break).
Another way of looking at this, is that those 6,000 devices have run for an average of two years. That makes it 12,000 device years. Or if one failed right now, that would be 9.5 FIT. So, under normal conditions, the failure rate is much less than 9.5 FIT.
To get a statistically significant number, the HTOL conditions place the device under conditions it should never see. This totally arbritray test method is the industry standard, and doesn't predict the real failure rate well at all. It will indicate if a part is in trouble, however, as a part will fail the HTOL qualification miserably if there is a weakness.