OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)

Hi

Xilinx FPGA's are nice but all of them (after XC4K?) do not have any more access to the OnChipOscillator - it is not usually required also, but in some rare cases it may be useful to have some OnChip Clock available in case all external clock sources fail, or do have emergency Watchdog timer to monitor some events also in the case of external clock circuitry failures. For this purpose we are developing OnChip Oscillator IP Cores.

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Simple Spartan-3 version is available, it delivers stable 1:1 duty ratio clock what is in the range of 205-220MHz for S3 -4 speedgrade. Special versions for other Xilinx families are coming shortly.

Antti PS to my surprise Lattice EC/XP and also MachXO all have access to their OnChip Oscillator, so at least in thing Xilinx FPGAs have less features available to the user.

Reply to
Antti Lukats
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Just looked at the sources - There are binary VHDL files. What does this mean?

Martin

Reply to
Martin Schoeberl

"Martin Schoeberl" schrieb im Newsbeitrag news:42e540a2$0$8024$ snipped-for-privacy@tunews.univie.ac.at...

more

case

failures.

This means they can only be used by ISE tools. There should be no problems using those files with ISE 6.2 to 7.1, just add to your project and synthesise as normal. If there are any problems let me know.

Antti

Reply to
Antti Lukats

Interesting - any data on Vcc and temp variations, and on other frequencies ?

Power consumption ? Seems to me, it would be better to create a clock as low as possible, before driving the high-load clock buffers. - thus a cell that is both OSC and Divider could be better ?

An advantage of on chip Osc, is they self-margin, so track Vcc and Temp. If I've understood your results, they show quite close correlation across the die.

This would also be a good way to see if faster speed grades REALLY are faster, or just stamped to match the market :)

?! - do you mean you cannot save as ASCII source code, or use any other editor ? Surely this nonsense can be disabled ?

-jg

Reply to
Jim Granville

see comments below

"Jim Granville" schrieb im Newsbeitrag news:42e58544$ snipped-for-privacy@clear.net.nz...

in

the OnChip Oscillator is part of larger project and yes we do some measurements, the vcc-temp variatans measurements are not done yet.

I only have measured some 5% frequency change in V4 when the chips temp raises from ambient to normal working temp.

But the maximal variation can actually be indirectly be calculated from Xilinx datasheets, from my estimate the frwquency should not be off more than +-20% over full temp and vcc range or xilinx datasheet values would not much - that comes from the margin in timing specs in datasheets.

of course this applies for one given device-speed grade combination and should be measured in the same CLB location

This cell is OSC and Divider by 2, the high speed signal path (about 440MHz) is kept completly inside the routing switch of an single CLB, ie it is not driving any short or long connections at all, only goes to swithcbox and back. The only load on this net is Divide by stage, what is the actual output of the OCO Cell.

we are developing OCO cells with low clock output as well, more suitable for things like watchdog, etc..

you understand correctly, the frequencies shown in the screenshot are from different CLB locations accross the die, and the correlation is about what was to be expected.

Yes, you are a mindreader - this is part of FPGA fine tuning project exactly targetted for timinig measurements of the FPGA internals.

problems

Sure, ask for commercial licensing and you will get readable source code instantly. At the moment the sources are encrypted to prevent modification.

Antti

Reply to
Antti Lukats

I think I miss-understood your first reply - I thought this was some new 'ISE feature', but it seems it is something you can enable/disable, to password IP sources, until paid - correct ?

-jg

Reply to
Jim Granville

problems

correct. until paid for source license.

Antti

Reply to
Antti Lukats

..and the price for that is.. ?

-jg

Reply to
Jim Granville

ok, as you asked then introductory offer -

1 company wide source code use license for the OCO library components for Spartan-3 2 free license for the clock analyzer application so you can perform the measurement accross chips and vcc/temp as needed 3 free license for the freq measurement ip cores (for the sw app) 4 free update/updgrade for Spartan-3E - as soon as we get S3E silicon for measurements and testing 5 tech support for instantition and use of the ip cores (per email) ==== 50 USD per paypal to snipped-for-privacy@openchip.org

Antti

Reply to
Antti Lukats

how often does an external clock fail? what king of the clock is it? how much useful to have an FPGA to backup?

-Franklin

Reply to
Franklin

"Franklin" schrieb im Newsbeitrag news: snipped-for-privacy@f14g2000cwb.googlegroups.com...

You are asking questions I dont have answers for, some possible uses I could have figured out for OCO use are:

1 External is not supposed to fail, but if as example the external clock was not soldered to PCB at all, then OCO could deliver backup clock for selfdiagnastic. 2 If external clock is coming from external programmable clock IC/PLL, then reprogramming it from FPGA may disable the output, and those making it impossible to recover (without backup clock) 3 for some initialization procedure it may be required to used clocked processes in FPGA before the external clock starts or DCMs lock 4 a Watchdog shoud generically not be clocked from main system clock 5 die temperature measurement, can be also done to measure temp in different places accross the die 6 fpga speed grade measurements, vcc and temp degration measurements

I think there are many more uses.

Besides - Lattice has FPGA onchip oscillator user accessible in all FPGA's, Altera has it available in MAX2, Xilinx had it available in XC4K, so I am just making it again available in new Xilinx FPGA's. Its not me who needs to figure out what todo it - I only provide the IP Cores and some characterization data. Its up to to ultimate user to find out it is useable and useful.

Just one example - I think Ray Andraka is one person who keeps saying 'do not use F5 mux' - its slowing down the performance. But how many people know how much the F5MUX penalty really is? This can be measuered easily with our IP Cores and tools with very high precision, without any special equipment, only special Software and JTAG cable is required. You can calc it yourself - a OCO with '2 logic delays' runs 210MHz, an OCO with 2 logic delays + F5 delay runs at 170MHz. This data is for S3 speedgrade -4. I havent calculated the F5 delay myself, but from the % of change I would say it is pretty significant. And that Ray is VERY right (as always) about the F5mux to be an evil when it goes high speed design optimization. To my knowledge Xilinx tools to not count the F5 delay in 'LUT logic levels' so knowing the penalty and carefully checking the F5 use and redesigning/constraininig a design better may give the needed performance boost for some designs.

Antti PS one very funny sample application is no components touch sensor - a plastic packaged FPGA can sense what side of the FPGA package you touch with your finger. So you can as example build an code-lock by using FPGA package as finger touch sensor. It is possible.

Reply to
Antti Lukats

External clock elimination is another clear usage area. There are many apps that do not care too greatly about the internal clock speed, so they can eliminate the external clock.

Others might use a (eg) 32Khz low power external Timebase, and run the FPGA as fast as possible, before re-idle.

Still others can AutoBAUD, or self calibrate to incomming data streams. The LIN bus specs such a preamble, designed for low performance oscillators.

-jg

Reply to
Jim Granville

You can make a ring oscillator in the FPGA with little trouble. No guarantees on the frequency, but you can nail it down to a frequency range that isn't going to vary by more than maybe +/-50% or so. That is quite useful in cases where you don't care much about frequency accuracy or stability. One application for a ring oscillator is the NBTI prevention circuit for the DCMs to keep them from degrading the performance when powered up without a clock. The fact that your frequency apparently shifts in the presence of a finger tells me you are just using a ring oscillator, possibly with a divider.

BTW, I don't believe I said don't use F5MUXs, I said I generally don't use them in high speed designs. I also don't use a second layer of LUTs without a flip-flop in between when I am worried about performance. Given the choice between going to two layers of 4LUTs or using an F5MUX, assuming for some reason I can't rearrange the logic or pipelining to knock the logic down to 4LUTs, I'll use the F5MUX because it has shorter and more predictable timing than a second layer of logic has. One of the beefs I have with the F5MUX is that it messes up the bit pitch in the layout. The 5 input logic takes up a slice, which is normally used for 2 bits, so you need to get a little more clever in the layout.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
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Ray Andraka

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