Hello,
I have 2 32x512 brams. I'm using the parity bits to extend the available data out a couple extra bits, so I can write a 66 bit word to the ram (designed with Xilinx's core generator). Only problem is when I try to specify what bits what go what bram in the bmm file, I get an error that I'm exceeding the maximum data length. Is there some way to specify in the bmm file that a couple of the bits are connected to the parity pins? My bmm file is below:
ADDRESS_BLOCK capture_ram RAMB16 [0x00040400:0x000407FF] BUS_BLOCK INST_CAPRAM/B6 [35:0] ; INST_CAPRAM/B10 [65:36] ; END_BUS_BLOCK; END_ADDRESS_BLOCK;
I get the following errors: ERROR:Data2MEM:26 - Illegal bit lane width in ADDRESS_SPACE 'capture_ram'. 'INST_CAPRAM/B6 [35:0]' is by 36. Only 1, 2, 4, 8, 16, 32 is allowed.
ERROR:Data2MEM:29 - Inconsistent address space size in ADDRESS_SPACE 'capture_ram'. ADDRESS_SPACE was defined as 0x000000400 bytes, but the devices total
0x000000000 bytes.
Any ideas to get around this? Thanks,
-- Matt
+-- |Matthew Plante | University of New Hampshire | InterOperability Lab | Research & Development | SMTP: snipped-for-privacy@iol.unh.edu | Phone: +1-603-862-0203
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