Hello all,
This issue has been here for a few times, so...
I was wondering if there is a progress with an issue of portability error during timing-driven packing and placement and when this fix is going to be released. Usually, I was able to manage without it, but now I have a design which is barely meeting the timing without it (it was previously doing good with it)
Thank you
Vladislav
Hi Vladislav,
with ISE7.1 SP3 I have seen the timing-driven p+p work on some designs. It even works on my own design, except when I use the option "register duplication" (-> results in that dreadful portability error). When I leave out all differential buffers in my design, it sudenly works. Unfortunately that's not really an option of course for my differential clock inputs :-(
What I'm trying to say : apparently there's lots of bad combinations that can trigger the portability error. My suggestion : just try it for your design. If it doesn't => open a webcase or contact your FAE, the more noise we make, the sooner it will get fixed (I hope).
best regards, Bart
Bart,
I am so sorry I forgot to add that I am using 7.1 SP3 and I am able to make timing driven PiP working by turning off "reg. dupl." :)
I was just wondering if there is a progress with it, as I have to pipeline parts of the design to meet timing.
I have opened a case and i was told that this is a known issue, so if i do not send my NGC/EDF, in 2 business days case closed --> completely understandable. Speaking about the noise... This is a noise!
Thanks!!!
Vladislav
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