wishbone core with ethernet, hierarchy / architecture

Hello, I am pretty new to working with FPGAs and verilog in general but have a decent knowledge of programming, and Im trying to grasp the whole concept of working with the wishbone, as well as verilog architecture. I have the wishbone commax core and the ethernet ip core from opencores.org, and im wondering how to go about setting up a basic system to have some ethernet communication coming from my board which currently is a Virtex-4 board , with a PHY chip built onto it. I know the cores themselves already have a great setup, but im still unclear on how to just place it all together. Im going to keep trying to play around with it more and dig around more to see exactly how to do this, but im the meaintime some sort of basic example of how to go about setting it up would be greatly appreciated. Im not looking for code as much as im looking for just a genereal layout of the hierarchy that I could use in ISE (which im using for programming atm).

Thank you for your time, Weizbox

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