Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

Good intro books on OFDM?

I'm a digital ASIC engineer looking for some *beginner* (not reference/advanced!) books on Orthogonal Frequency Divisio...
5 comments posted 21yrs
posted by whatisofdm
5 comments posted 21yrs posted by whatisofdm

Xilinx Impact order

Hello group, I've got 3 Spartans and three platform PROMs in my JTAG daisy chain. Now I can load the first Xilinx fine,...
6 comments posted 21yrs
posted by bradsmallridge
6 comments posted 21yrs posted by bradsmallridge

Anyone had this error / knows what it means?

ERROR:Xst: 1706 - Node , from parent , has no source for port Dear All, When synthesising my VHDL code in the Xilinx IS...
0 comments posted 21yrs
posted by simon.stockton
0 comments posted 21yrs posted by simon.stockton

Auto generation of memory files

Hi, I was wanting to know if there was a way to auto-generate a mif or hexout file in quartus (or in general verilog) b...
7 comments posted 21yrs
posted by psolomon
7 comments posted 21yrs posted by psolomon

Where can i find GeneticFPGA toolkit

Hello Everyone I am a final year student at Manukau Institute of Technology.I am doing my honours research project on E...
17 comments posted 21yrs
posted by apsolar
17 comments posted 21yrs posted by apsolar

Quartus II 4.2 Incremental Systhesis

Hi, I am currently using the evaluation open-core FIR compiler and NCO compiler in the design and when I use these I am...
2 comments posted 21yrs
posted by psolomon
2 comments posted 21yrs posted by psolomon

3.3V tolerant configuration interface Spartan 3

This is with reference to page 33 of Xilinx's Spartan 3 Family: Functional Description. Paraphrasing from the documenta...
1 comments posted 21yrs
posted by yaj_n
1 comments posted 21yrs posted by yaj_n

Modulation Clock to set FPGA timing

I am looking for some help in regards to a 20 MHz modulation clock that needs to set the timing in the Virtex_II_Pro. I...
5 comments posted 21yrs
posted by cyd
5 comments posted 21yrs posted by cyd

System Engineering in the R/D World

Hello, I couldn't find a single newsgroup to post my question, but I needed a good group of people to post my question...
44 comments posted 21yrs
posted by jjlindula
44 comments posted 21yrs posted by jjlindula

Legality of type conversion on instance ports?

I'm experiencing an error using XST during synthesis involving a type conversion on a port instance: http://www.xilinx....
4 comments posted 21yrs
posted by killerhertz
4 comments posted 21yrs posted by killerhertz

How to import EDIF netlist into ISE webpack 7.1

Hallo, I am a newbie evaluating xilinx tools & FPGAs for our project.Our company traditionally uses altera.We have boug...
4 comments posted 21yrs
posted by monica_dsz
4 comments posted 21yrs posted by monica_dsz

RocketIO connexion to an optical transceiver

Hi, I work on a project involving an optical link. The transceiver is a finisar one with a CML interface and AC coupled...
13 comments posted 21yrs
posted by j-f.hasson
13 comments posted 21yrs posted by j-f.hasson

Area Group IOB Range

Hi I'm trying to put an IOB range contraint on an AREA_GROUP I did the following: AREA_GROUP "GRP0" RANGE = A2:A25; But...
2 comments posted 21yrs
posted by Hua.Zheng
2 comments posted 21yrs posted by Hua.Zheng

5V non-volatile reprogrammable FPGA/CPLD

What are the 5V or 5V tolerant options for non-volatile, reprogrammable, In System Programmable logic, capable of stori...
4 comments posted 21yrs
posted by mitrusc1980-newsgroup
4 comments posted 21yrs posted by mitrusc1980-newsgroup